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st sitronix ST7669V 262k 132 x 162 color dot matrix lcd controller/driver ver 1.3 1/208 6/4/2008 1 introduction the ST7669V is a driver & controller lsi for 262k colo r graphic dot-matrix liquid crystal display systems . it generates 396 segments and 162 common driver circuits. this chip is connected directly to a microprocessor, accepts serial peripheral interface or 8-bit/16-bit/18-bit parallel display d ata and stores in an on-chip display data ram. it p erforms display data ram read/write operation with no external operating clo ck to minimize power consumption. in addition, beca use it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fe west components. 2 features driver output circuits 396 segment outputs / 162 common outputs applicable duty ratios various partial display partial window moving & data scrolling gray-scale display 4frc & 31 pwm function circuit to display 64 gray-s cale display support 8 color mode (idle mode) on-chip display data ram capacity: 132 x 162 x 18 = 384,912 bits color support by interface 256 color mode(rgb)=(332) mode 4k colors (rgb)=(444) mode 65k colors (rgb)=(565) mode 262k colors (rgb)=(666) mode microprocessor interface 8/16/18-bit parallel bi-directional interface with 6800-series or 8080-series 3-line (9-bits) , 4-line(8-bits) serial interface on-chip low power analog circuit on-chip oscillator circuit and voltage regulator voltage converter (x1, x2, x3, x4, x5, x6, x7, x8) with internal booster capacitors. extremely few outsider components. (required outsi der components: 3 capacitors) on-chip electronic contrast control function voltage follower (lcd bias: 1/5, 1/7, 1/9, 1/10, 1/11, 1/12, 1/13, 1/14) operating voltage range supply digital voltage (vdd): 1.65v to 3.0v supply analog voltage (vdd2, vdd3, vdd4, vdd5): 2.4 to 3.3v lcd driving voltage (vop = v0 - vss): max: 18v lcd driving voltage (otpc) contrast adjustment value is stored in the built-in otp-rom for better display quality lcd driving setting suggestion bias = 1/9, vop = 15v bias = 1/10 or 1/11, vop = 16.5v package type application for cog ST7669V-g3 chip thickness=400um ST7669V-g4 chip thickness=300um 6800, 8080 , 4-line, 3-line interface sitronix technology corp. reserves the right to chan ge the contents in this document without prior noti ce.
ST7669V ver 1.3 2/208 6/4/2008 3 pad arrangement (cog) chip size : 14030 um x 970 um bump pitch : pad 1 ~ 30, 31 ~ 35 pitch=27um(min, com/seg) pad 200 ~ 204, 205 ~ 737 pitch=27um(min, com/seg) pad 36 ~ 199 pitch=80um (i/o) pad 87,88 pitch= 79.72um(i/o) bump size : pad 1 ~ 35 , pad 200 ~ 737 bump width=14um(min, com/seg) bump space=13um(min, com/seg) bump length=128um(min, com/seg) bump area=1800um^2(com/seg) pad 36 ~86,89~199(except 87,88) bump width=65um(i/o) bump space=15um(i/o) bump length=63um(i/o) bump area=4095um^2 pad 87,88 bump width=65um(i/o) bump space=14.72um(i/o) bump length=63um(i/o) bump area=4095um^2 bump height : 15 um alignment mark the center of alignment mark: see bellow table
ST7669V ver 1.3 3/208 6/4/2008 4 pad center coordinates pad name x y 1 tluo -6897.71 421.50 2 tlui -6897.71 394.50 3 com58 -6897.71 337.50 4 com56 -6897.71 310.50 5 com54 -6897.71 283.50 6 com52 -6897.71 256.50 7 com50 -6897.71 229.50 8 com48 -6897.71 202.50 9 com46 -6897.71 175.50 10 com44 -6897.71 148.50 11 com42 -6897.71 121.50 12 com40 -6897.71 94.50 13 com38 -6897.71 67.50 14 com36 -6897.71 40.50 15 com34 -6897.71 13.50 16 com32 -6897.71 -13.50 17 com30 -6897.71 -40.50 18 com28 -6897.71 -67.50 19 com26 -6897.71 -94.50 20 com24 -6897.71 -121.50 21 com22 -6897.71 -148.50 22 com20 -6897.71 -175.50 23 com18 -6897.71 -202.50 24 com16 -6897.71 -229.50 25 com14 -6897.71 -256.50 26 com12 -6897.71 -283.50 27 com10 -6897.71 -310.50 28 com8 -6897.71 -337.50 29 tlbi -6897.71 -394.50 30 tlbo -6897.71 -421.50 31 com6 -6749.45 -367.71 32 com4 -6722.45 -367.71 33 com2 -6695.45 -367.71 34 com0 -6668.45 -367.71 35 tgi -6608.30 -367.71 36 dummy -6491.97 -394.50 37 dummy -6411.97 -394.50 38 dummy -6331.97 -394.50 39 vss -6251.97 -394.50 40 vpp -6171.97 -394.50 41 vpp -6091.97 -394.50 42 vpp -6011.97 -394.50 43 vpp -5931.97 -394.50 44 dummy -5851.97 -394.50 45 dummy -5771.97 -394.50 46 dummy -5691.97 -394.50 47 dummy -5611.97 -394.50 48 dummy -5531.97 -394.50 49 dummy -5451.97 -394.50 50 dummy -5371.97 -394.50 51 dummy -5291.97 -394.50 52 dummy -5211.97 -394.50 53 dummy -5131.97 -394.50 54 dummy -5051.97 -394.50 55 dummy -4971.97 -394.50 56 dummy -4891.97 -394.50 57 dummy -4811.97 -394.50 58 dummy -4731.97 -394.50 59 dummy -4651.97 -394.50 60 dummy -4571.97 -394.50 61 dummy -4491.97 -394.50 62 dummy -4411.97 -394.50 63 dummy -4331.97 -394.50 64 dummy -4251.97 -394.50 65 dummy -4171.97 -394.50 66 dummy -4091.97 -394.50 67 vm -4011.97 -394.50 68 vm -3931.97 -394.50 69 vm -3851.97 -394.50 70 vm -3771.97 -394.50
ST7669V ver 1.3 4/208 6/4/2008 71 vm -3691.97 -394.50 72 vm -3611.97 -394.50 73 vm -3531.97 -394.50 74 vm -3451.97 -394.50 75 dummy -3371.97 -394.50 76 dummy -3291.97 -394.50 77 dummy -3211.97 -394.50 78 dummy -3131.97 -394.50 79 dummy -3051.97 -394.50 80 dummy -2971.97 -394.50 81 dummy -2891.97 -394.50 82 dummy -2811.97 -394.50 83 dummy -2731.97 -394.50 84 dummy -2651.97 -394.50 85 dummy -2571.97 -394.50 86 cl -2491.97 -394.50 87 cls -2411.97 -394.50 88 vdd -2332.25 -394.50 89 a0 -2252.25 -394.50 90 rw_wr -2172.25 -394.50 91 d0 -2092.25 -394.50 92 d1 -2012.25 -394.50 93 d2 -1932.25 -394.50 94 d3 -1852.25 -394.50 95 d4 -1772.25 -394.50 96 d5 -1692.25 -394.50 97 d6 -1612.25 -394.50 98 d7 -1532.25 -394.50 99 d8 -1452.25 -394.50 100 d9 -1372.25 -394.50 101 d10 -1292.25 -394.50 102 d11 -1212.25 -394.50 103 d12 -1132.25 -394.50 104 d13 -1052.25 -394.50 105 d14 -972.25 -394.50 106 d15 -892.25 -394.50 107 d16 -812.25 -394.50 108 d17 -732.25 -394.50 109 vss -652.25 -394.50 110 vdd -572.25 -394.50 111 e_rd -492.25 -394.50 112 /rst -412.25 -394.50 113 csel -332.25 -394.50 114 if1 -252.25 -394.50 115 if2 -172.25 -394.50 116 if3 -92.25 -394.50 117 vss -12.25 -394.50 118 vdd 67.75 -394.50 119 /cs 147.75 -394.50 120 /ext 227.75 -394.50 121 te 307.75 -394.50 122 tcap 387.75 -394.50 123 vdd 467.75 -394.50 124 vdd 547.75 -394.50 125 vdd 627.75 -394.50 126 vdd 707.75 -394.50 127 vdd 787.75 -394.50 128 vdd 867.75 -394.50 129 vss1 947.75 -394.50 130 vss1 1027.75 -394.50 131 vss 1107.75 -394.50 132 vss 1187.75 -394.50 133 vss 1267.75 -394.50 134 vss 1347.75 -394.50 135 vss2 1427.75 -394.50 136 vss2 1507.75 -394.50 137 vss2 1587.75 -394.50 138 vss2 1667.75 -394.50 139 vss2 1747.75 -394.50 140 vss2 1827.75 -394.50
ST7669V ver 1.3 5/208 6/4/2008 141 vss2 1907.75 -394.50 142 vss2 1987.75 -394.50 143 vss2 2067.75 -394.50 144 vss2 2147.75 -394.50 145 vss2 2227.75 -394.50 146 vss2 2307.75 -394.50 147 vss4 2387.75 -394.50 148 vss4 2467.75 -394.50 149 vdd3 2547.75 -394.50 150 vdd3 2627.75 -394.50 151 vdd4 2707.75 -394.50 152 vdd4 2787.75 -394.50 153 vdd5 2867.75 -394.50 154 vdd5 2947.75 -394.50 155 vdd5 3027.75 -394.50 156 vdd5 3107.75 -394.50 157 vdd5 3187.75 -394.50 158 vdd5 3267.75 -394.50 159 vdd5 3347.75 -394.50 160 vdd5 3427.75 -394.50 161 vdd2 3507.75 -394.50 162 vdd2 3587.75 -394.50 163 vdd2 3667.75 -394.50 164 vdd2 3747.75 -394.50 165 vdd2 3827.75 -394.50 166 vdd2 3907.75 -394.50 167 vdd2 3987.75 -394.50 168 vdd2 4067.75 -394.50 169 vdd2 4147.75 -394.50 170 vdd2 4227.75 -394.50 171 vm 4307.75 -394.50 172 vref 4387.75 -394.50 173 v0in 4467.75 -394.50 174 v0in 4547.75 -394.50 175 v0in 4627.75 -394.50 176 v0in 4707.75 -394.50 177 v0s 4787.75 -394.50 178 v0out 4867.75 -394.50 179 v0out 4947.75 -394.50 180 xv0out 5027.75 -394.50 181 xv0out 5107.75 -394.50 182 xv0s 5187.75 -394.50 183 xv0in 5267.75 -394.50 184 xv0in 5347.75 -394.50 185 xv0in 5427.75 -394.50 186 xv0in 5507.75 -394.50 187 vgout 5587.75 -394.50 188 vgout 5667.75 -394.50 189 vgs 5747.75 -394.50 190 vgin 5827.75 -394.50 191 vgin 5907.75 -394.50 192 vgin 5987.75 -394.50 193 vgin 6067.75 -394.50 194 vgin 6147.75 -394.50 195 vgin 6227.75 -394.50 196 vgin 6307.75 -394.50 197 vgin 6387.75 -394.50 198 vss 6467.75 -394.50 199 dummy 6547.75 -394.50 200 tgo 6608.30 -367.71 201 com1 6668.45 -367.71 202 com3 6695.45 -367.71 203 com5 6722.45 -367.71 204 com7 6749.45 -367.71 205 trbo 6897.71 -421.50 206 trbi 6897.71 -394.50 207 com9 6897.71 -337.50 208 com11 6897.71 -310.50 209 com13 6897.71 -283.50 210 com15 6897.71 -256.50
ST7669V ver 1.3 6/208 6/4/2008 211 com17 6897.71 -229.50 212 com19 6897.71 -202.50 213 com21 6897.71 -175.50 214 com23 6897.71 -148.50 215 com25 6897.71 -121.50 216 com27 6897.71 -94.50 217 com29 6897.71 -67.50 218 com31 6897.71 -40.50 219 com33 6897.71 -13.50 220 com35 6897.71 13.50 221 com37 6897.71 40.50 222 com39 6897.71 67.50 223 com41 6897.71 94.50 224 com43 6897.71 121.50 225 com45 6897.71 148.50 226 com47 6897.71 175.50 227 com49 6897.71 202.50 228 com51 6897.71 229.50 229 com53 6897.71 256.50 230 com55 6897.71 283.50 231 com57 6897.71 310.50 232 com59 6897.71 337.50 233 trui 6897.71 394.50 234 truo 6897.71 421.50 235 com61 6743.18 367.71 236 com63 6716.18 367.71 237 com65 6689.18 367.71 238 com67 6662.18 367.71 239 com69 6635.18 367.71 240 l-mark 6593.69 234.18 241 com71 6608.18 367.71 242 l-mark 6593.69 234.18 243 l-mark 6593.69 234.18 244 com73 6581.18 367.71 245 com75 6554.18 367.71 246 com77 6527.18 367.71 247 com79 6500.18 367.71 248 com81 6473.18 367.71 249 com83 6446.18 367.71 250 com85 6419.18 367.71 251 com87 6392.18 367.71 252 com89 6365.18 367.71 253 com91 6338.18 367.71 254 com93 6311.18 367.71 255 com95 6284.18 367.71 256 com97 6257.18 367.71 257 com99 6230.18 367.71 258 com101 6203.18 367.71 259 com103 6176.18 367.71 260 com105 6149.18 367.71 261 com107 6122.18 367.71 262 com109 6095.18 367.71 263 com111 6068.18 367.71 264 com113 6041.18 367.71 265 com115 6014.18 367.71 266 com117 5987.18 367.71 267 com119 5960.18 367.71 268 com121 5933.18 367.71 269 com123 5906.18 367.71 270 com125 5879.18 367.71 271 com127 5852.18 367.71 272 com129 5825.18 367.71 273 com131 5798.18 367.71 274 com133 5771.18 367.71 275 com135 5744.18 367.71 276 com137 5717.18 367.71 277 com139 5690.18 367.71 278 com141 5663.18 367.71 279 com143 5636.18 367.71 280 com145 5609.18 367.71
ST7669V ver 1.3 7/208 6/4/2008 281 com147 5582.18 367.71 282 com149 5555.18 367.71 283 com151 5528.18 367.71 284 com153 5501.18 367.71 285 com155 5474.18 367.71 286 com157 5447.18 367.71 287 com159 5420.18 367.71 288 com161 5393.18 367.71 289 seg0 5332.50 367.71 290 seg1 5305.50 367.71 291 seg2 5278.50 367.71 292 seg3 5251.50 367.71 293 seg4 5224.50 367.71 294 seg5 5197.50 367.71 295 seg6 5170.50 367.71 296 seg7 5143.50 367.71 297 seg8 5116.50 367.71 298 seg9 5089.50 367.71 299 seg10 5062.50 367.71 300 seg11 5035.50 367.71 301 seg12 5008.50 367.71 302 seg13 4981.50 367.71 303 seg14 4954.50 367.71 304 seg15 4927.50 367.71 305 seg16 4900.50 367.71 306 seg17 4873.50 367.71 307 seg18 4846.50 367.71 308 seg19 4819.50 367.71 309 seg20 4792.50 367.71 310 seg21 4765.50 367.71 311 seg22 4738.50 367.71 312 seg23 4711.50 367.71 313 seg24 4684.50 367.71 314 seg25 4657.50 367.71 315 seg26 4630.50 367.71 316 seg27 4603.50 367.71 317 seg28 4576.50 367.71 318 seg29 4549.50 367.71 319 seg30 4522.50 367.71 320 seg31 4495.50 367.71 321 seg32 4468.50 367.71 322 seg33 4441.50 367.71 323 seg34 4414.50 367.71 324 seg35 4387.50 367.71 325 seg36 4360.50 367.71 326 seg37 4333.50 367.71 327 seg38 4306.50 367.71 328 seg39 4279.50 367.71 329 seg40 4252.50 367.71 330 seg41 4225.50 367.71 331 seg42 4198.50 367.71 332 seg43 4171.50 367.71 333 seg44 4144.50 367.71 334 seg45 4117.50 367.71 335 seg46 4090.50 367.71 336 seg47 4063.50 367.71 337 seg48 4036.50 367.71 338 seg49 4009.50 367.71 339 seg50 3982.50 367.71 340 seg51 3955.50 367.71 341 seg52 3928.50 367.71 342 seg53 3901.50 367.71 343 seg54 3874.50 367.71 344 seg55 3847.50 367.71 345 seg56 3820.50 367.71 346 seg57 3793.50 367.71 347 seg58 3766.50 367.71 348 seg59 3739.50 367.71 349 seg60 3712.50 367.71 350 seg61 3685.50 367.71
ST7669V ver 1.3 8/208 6/4/2008 351 seg62 3658.50 367.71 352 seg63 3631.50 367.71 353 seg64 3604.50 367.71 354 seg65 3577.50 367.71 355 seg66 3550.50 367.71 356 seg67 3523.50 367.71 357 seg68 3496.50 367.71 358 seg69 3469.50 367.71 359 seg70 3442.50 367.71 360 seg71 3415.50 367.71 361 seg72 3388.50 367.71 362 seg73 3361.50 367.71 363 seg74 3334.50 367.71 364 seg75 3307.50 367.71 365 seg76 3280.50 367.71 366 seg77 3253.50 367.71 367 seg78 3226.50 367.71 368 seg79 3199.50 367.71 369 seg80 3172.50 367.71 370 seg81 3145.50 367.71 371 seg82 3118.50 367.71 372 seg83 3091.50 367.71 373 seg84 3064.50 367.71 374 seg85 3037.50 367.71 375 seg86 3010.50 367.71 376 seg87 2983.50 367.71 377 seg88 2956.50 367.71 378 seg89 2929.50 367.71 379 seg90 2902.50 367.71 380 seg91 2875.50 367.71 381 seg92 2848.50 367.71 382 seg93 2821.50 367.71 383 seg94 2794.50 367.71 384 seg95 2767.50 367.71 385 seg96 2740.50 367.71 386 seg97 2713.50 367.71 387 seg98 2686.50 367.71 388 seg99 2659.50 367.71 389 seg100 2632.50 367.71 390 seg101 2605.50 367.71 391 seg102 2578.50 367.71 392 seg103 2551.50 367.71 393 seg104 2524.50 367.71 394 seg105 2497.50 367.71 395 seg106 2470.50 367.71 396 seg107 2443.50 367.71 397 seg108 2416.50 367.71 398 seg109 2389.50 367.71 399 seg110 2362.50 367.71 400 seg111 2335.50 367.71 401 seg112 2308.50 367.71 402 seg113 2281.50 367.71 403 seg114 2254.50 367.71 404 seg115 2227.50 367.71 405 seg116 2200.50 367.71 406 seg117 2173.50 367.71 407 seg118 2146.50 367.71 408 seg119 2119.50 367.71 409 seg120 2092.50 367.71 410 seg121 2065.50 367.71 411 seg122 2038.50 367.71 412 seg123 2011.50 367.71 413 seg124 1984.50 367.71 414 seg125 1957.50 367.71 415 seg126 1930.50 367.71 416 seg127 1903.50 367.71 417 seg128 1876.50 367.71 418 seg129 1849.50 367.71 419 seg130 1822.50 367.71 420 seg131 1795.50 367.71
ST7669V ver 1.3 9/208 6/4/2008 421 seg132 1768.50 367.71 422 seg133 1741.50 367.71 423 seg134 1714.50 367.71 424 seg135 1687.50 367.71 425 seg136 1660.50 367.71 426 seg137 1633.50 367.71 427 seg138 1606.50 367.71 428 seg139 1579.50 367.71 429 seg140 1552.50 367.71 430 seg141 1525.50 367.71 431 seg142 1498.50 367.71 432 seg143 1471.50 367.71 433 seg144 1444.50 367.71 434 seg145 1417.50 367.71 435 seg146 1390.50 367.71 436 seg147 1363.50 367.71 437 seg148 1336.50 367.71 438 seg149 1309.50 367.71 439 seg150 1282.50 367.71 440 seg151 1255.50 367.71 441 seg152 1228.50 367.71 442 seg153 1201.50 367.71 443 seg154 1174.50 367.71 444 seg155 1147.50 367.71 445 seg156 1120.50 367.71 446 seg157 1093.50 367.71 447 seg158 1066.50 367.71 448 seg159 1039.50 367.71 449 seg160 1012.50 367.71 450 seg161 985.50 367.71 451 seg162 958.50 367.71 452 seg163 931.50 367.71 453 seg164 904.50 367.71 454 seg165 877.50 367.71 455 seg166 850.50 367.71 456 seg167 823.50 367.71 457 seg168 796.50 367.71 458 seg169 769.50 367.71 459 seg170 742.50 367.71 460 seg171 715.50 367.71 461 seg172 688.50 367.71 462 seg173 661.50 367.71 463 seg174 634.50 367.71 464 seg175 607.50 367.71 465 seg176 580.50 367.71 466 seg177 553.50 367.71 467 seg178 526.50 367.71 468 seg179 499.50 367.71 469 seg180 472.50 367.71 470 seg181 445.50 367.71 471 seg182 418.50 367.71 472 seg183 391.50 367.71 473 seg184 364.50 367.71 474 seg185 337.50 367.71 475 seg186 310.50 367.71 476 seg187 283.50 367.71 477 seg188 256.50 367.71 478 seg189 229.50 367.71 479 seg190 202.50 367.71 480 seg191 175.50 367.71 481 seg192 148.50 367.71 482 seg193 121.50 367.71 483 seg194 94.50 367.71 484 seg195 67.50 367.71 485 seg196 40.50 367.71 486 seg197 13.50 367.71 487 seg198 -13.50 367.71 488 seg199 -40.50 367.71 489 seg200 -67.50 367.71 490 seg201 -94.50 367.71
ST7669V ver 1.3 10/208 6/4/2008 491 seg202 -121.50 367.71 492 seg203 -148.50 367.71 493 seg204 -175.50 367.71 494 seg205 -202.50 367.71 495 seg206 -229.50 367.71 496 seg207 -256.50 367.71 497 seg208 -283.50 367.71 498 seg209 -310.50 367.71 499 seg210 -337.50 367.71 500 seg211 -364.50 367.71 501 seg212 -391.50 367.71 502 seg213 -418.50 367.71 503 seg214 -445.50 367.71 504 seg215 -472.50 367.71 505 seg216 -499.50 367.71 506 seg217 -526.50 367.71 507 seg218 -553.50 367.71 508 seg219 -580.50 367.71 509 seg220 -607.50 367.71 510 seg221 -634.50 367.71 511 seg222 -661.50 367.71 512 seg223 -688.50 367.71 513 seg224 -715.50 367.71 514 seg225 -742.50 367.71 515 seg226 -769.50 367.71 516 seg227 -796.50 367.71 517 seg228 -823.50 367.71 518 seg229 -850.50 367.71 519 seg230 -877.50 367.71 520 seg231 -904.50 367.71 521 seg232 -931.50 367.71 522 seg233 -958.50 367.71 523 seg234 -985.50 367.71 524 seg235 -1012.50 367.71 525 seg236 -1039.50 367.71 526 seg237 -1066.50 367.71 527 seg238 -1093.50 367.71 528 seg239 -1120.50 367.71 529 seg240 -1147.50 367.71 530 seg241 -1174.50 367.71 531 seg242 -1201.50 367.71 532 seg243 -1228.50 367.71 533 seg244 -1255.50 367.71 534 seg245 -1282.50 367.71 535 seg246 -1309.50 367.71 536 seg247 -1336.50 367.71 537 seg248 -1363.50 367.71 538 seg249 -1390.50 367.71 539 seg250 -1417.50 367.71 540 seg251 -1444.50 367.71 541 seg252 -1471.50 367.71 542 seg253 -1498.50 367.71 543 seg254 -1525.50 367.71 544 seg255 -1552.50 367.71 545 seg256 -1579.50 367.71 546 seg257 -1606.50 367.71 547 seg258 -1633.50 367.71 548 seg259 -1660.50 367.71 549 seg260 -1687.50 367.71 550 seg261 -1714.50 367.71 551 seg262 -1741.50 367.71 552 seg263 -1768.50 367.71 553 seg264 -1795.50 367.71 554 seg265 -1822.50 367.71 555 seg266 -1849.50 367.71 556 seg267 -1876.50 367.71 557 seg268 -1903.50 367.71 558 seg269 -1930.50 367.71 559 seg270 -1957.50 367.71 560 seg271 -1984.50 367.71
ST7669V ver 1.3 11/208 6/4/2008 561 seg272 -2011.50 367.71 562 seg273 -2038.50 367.71 563 seg274 -2065.50 367.71 564 seg275 -2092.50 367.71 565 seg276 -2119.50 367.71 566 seg277 -2146.50 367.71 567 seg278 -2173.50 367.71 568 seg279 -2200.50 367.71 569 seg280 -2227.50 367.71 570 seg281 -2254.50 367.71 571 seg282 -2281.50 367.71 572 seg283 -2308.50 367.71 573 seg284 -2335.50 367.71 574 seg285 -2362.50 367.71 575 seg286 -2389.50 367.71 576 seg287 -2416.50 367.71 577 seg288 -2443.50 367.71 578 seg289 -2470.50 367.71 579 seg290 -2497.50 367.71 580 seg291 -2524.50 367.71 581 seg292 -2551.50 367.71 582 seg293 -2578.50 367.71 583 seg294 -2605.50 367.71 584 seg295 -2632.50 367.71 585 seg296 -2659.50 367.71 586 seg297 -2686.50 367.71 587 seg298 -2713.50 367.71 588 seg299 -2740.50 367.71 589 seg300 -2767.50 367.71 590 seg301 -2794.50 367.71 591 seg302 -2821.50 367.71 592 seg303 -2848.50 367.71 593 seg304 -2875.50 367.71 594 seg305 -2902.50 367.71 595 seg306 -2929.50 367.71 596 seg307 -2956.50 367.71 597 seg308 -2983.50 367.71 598 seg309 -3010.50 367.71 599 seg310 -3037.50 367.71 600 seg311 -3064.50 367.71 601 seg312 -3091.50 367.71 602 seg313 -3118.50 367.71 603 seg314 -3145.50 367.71 604 seg315 -3172.50 367.71 605 seg316 -3199.50 367.71 606 seg317 -3226.50 367.71 607 seg318 -3253.50 367.71 608 seg319 -3280.50 367.71 609 seg320 -3307.50 367.71 610 seg321 -3334.50 367.71 611 seg322 -3361.50 367.71 612 seg323 -3388.50 367.71 613 seg324 -3415.50 367.71 614 seg325 -3442.50 367.71 615 seg326 -3469.50 367.71 616 seg327 -3496.50 367.71 617 seg328 -3523.50 367.71 618 seg329 -3550.50 367.71 619 seg330 -3577.50 367.71 620 seg331 -3604.50 367.71 621 seg332 -3631.50 367.71 622 seg333 -3658.50 367.71 623 seg334 -3685.50 367.71 624 seg335 -3712.50 367.71 625 seg336 -3739.50 367.71 626 seg337 -3766.50 367.71 627 seg338 -3793.50 367.71 628 seg339 -3820.50 367.71 629 seg340 -3847.50 367.71 630 seg341 -3874.50 367.71
ST7669V ver 1.3 12/208 6/4/2008 631 seg342 -3901.50 367.71 632 seg343 -3928.50 367.71 633 seg344 -3955.50 367.71 634 seg345 -3982.50 367.71 635 seg346 -4009.50 367.71 636 seg347 -4036.50 367.71 637 seg348 -4063.50 367.71 638 seg349 -4090.50 367.71 639 seg350 -4117.50 367.71 640 seg351 -4144.50 367.71 641 seg352 -4171.50 367.71 642 seg353 -4198.50 367.71 643 seg354 -4225.50 367.71 644 seg355 -4252.50 367.71 645 seg356 -4279.50 367.71 646 seg357 -4306.50 367.71 647 seg358 -4333.50 367.71 648 seg359 -4360.50 367.71 649 seg360 -4387.50 367.71 650 seg361 -4414.50 367.71 651 seg362 -4441.50 367.71 652 seg363 -4468.50 367.71 653 seg364 -4495.50 367.71 654 seg365 -4522.50 367.71 655 seg366 -4549.50 367.71 656 seg367 -4576.50 367.71 657 seg368 -4603.50 367.71 658 seg369 -4630.50 367.71 659 seg370 -4657.50 367.71 660 seg371 -4684.50 367.71 661 seg372 -4711.50 367.71 662 seg373 -4738.50 367.71 663 seg374 -4765.50 367.71 664 seg375 -4792.50 367.71 665 seg376 -4819.50 367.71 666 seg377 -4846.50 367.71 667 seg378 -4873.50 367.71 668 seg379 -4900.50 367.71 669 seg380 -4927.50 367.71 670 seg381 -4954.50 367.71 671 seg382 -4981.50 367.71 672 seg383 -5008.50 367.71 673 seg384 -5035.50 367.71 674 seg385 -5062.50 367.71 675 seg386 -5089.50 367.71 676 seg387 -5116.50 367.71 677 seg388 -5143.50 367.71 678 seg389 -5170.50 367.71 679 seg390 -5197.50 367.71 680 seg391 -5224.50 367.71 681 seg392 -5251.50 367.71 682 seg393 -5278.50 367.71 683 seg394 -5305.50 367.71 684 seg395 -5332.50 367.71 685 com160 -5393.18 367.71 686 com158 -5420.18 367.71 687 com156 -5447.18 367.71 688 com154 -5474.18 367.71 689 com152 -5501.18 367.71 690 com150 -5528.18 367.71 691 com148 -5555.18 367.71 692 com146 -5582.18 367.71 693 com144 -5609.18 367.71 694 com142 -5636.18 367.71 695 com140 -5663.18 367.71 696 com138 -5690.18 367.71 697 com136 -5717.18 367.71 698 com134 -5744.18 367.71 699 com132 -5771.18 367.71 700 com130 -5798.18 367.71
ST7669V ver 1.3 13/208 6/4/2008 701 com128 -5825.18 367.71 702 com126 -5852.18 367.71 703 com124 -5879.18 367.71 704 com122 -5906.18 367.71 705 com120 -5933.18 367.71 706 com118 -5960.18 367.71 707 com116 -5987.18 367.71 708 com114 -6014.18 367.71 709 com112 -6041.18 367.71 710 com110 -6068.18 367.71 711 com108 -6095.18 367.71 712 com106 -6122.18 367.71 713 com104 -6149.18 367.71 714 com102 -6176.18 367.71 715 com100 -6203.18 367.71 716 com98 -6230.18 367.71 717 com96 -6257.18 367.71 718 com94 -6284.18 367.71 719 com92 -6311.18 367.71 720 com90 -6338.18 367.71 721 com88 -6365.18 367.71 722 com86 -6392.18 367.71 723 com84 -6419.18 367.71 724 com82 -6446.18 367.71 725 com80 -6473.18 367.71 726 com78 -6500.18 367.71 727 com76 -6527.18 367.71 728 com74 -6554.18 367.71 729 com72 -6581.18 367.71 730 l-mark -6593.69 234.18 731 l-mark -6593.69 234.18 732 com70 -6608.18 367.71 733 com68 -6635.18 367.71 734 com66 -6662.18 367.71 735 com64 -6689.18 367.71 736 com62 -6716.18 367.71 737 com60 -6743.18 367.71 738 l-mark 6593.69 -230.09
ST7669V ver 1.3 14/208 6/4/2008 5 block diagram
ST7669V ver 1.3 15/208 6/4/2008 6 pin description 6.1 power supply name i/o description vdd supply power supply for logic circuit (digital vdd 1.65v~3.0v) vdd2 supply power supply for booster circuit (analog vdd 2.4v~3.3v) vdd3 supply power supply for lcd. (analog vdd 2.4v~3.3v) vdd4 supply power supply for lcd. (analog vdd 2.4v~3.3v) vdd5 supply power supply for lcd. (analog vdd 2.4v~3.3v) vss supply ground for logic circuit. ground system sho uld be connected together. vss1 supply ground for osc circuit. ground system should be connected together. vss2 supply ground for booster circuit. ground system sh ould be connected together. vss4 supply ground for lcd. ground system should be conne cted together. 6.2 lcd power supply pins name i/o description v0 out v0 in v0 s i/o positive lcd driver supply voltages. v0 out is the output voltage of v0 generated by ST7669V. v0 in is the input pin of power supply to generate v0 vol tage for lcd. v0 s is the input pin of power supply to sense the v0 v oltage. v0 out , v0 in & v0 s should be connected together in fpc. xv0 out xv0 in xv0 s i/o negative lcd driver supply voltages. xv0 out is the output voltage of xv0 generated by ST7669V. xv0 in is the input pin of power supply to generate xv0 vo ltage for lcd. xv0 s is the input pin of power supply to sense the xv0 v oltage. xv0 out , xv0 in & xv0 s should be connected together in fpc. vg out vg in vg s vm i/o bias lcd driver supply voltages. vg out is the output voltage of vg generated by ST7669V. vg in is the input pin of power supply to generate vg vol tage for lcd. vg s is the input pin of power supply to sense the vg v oltage. vg out , vg in & vg s should be connected together in fpc. vm is the i/o pin of lcd bias supply voltage. voltages should have the following relationship; v0 vg vm vss xv0. R R R R and vdda-0.7v>vm>0.7v, 2xvdda R vg>1.8v when the internal power circuit is active, these vo ltages are generated as following table according to the state of lcd bias. note: n = 5,7,9,10,11,12,13 and 14 lcd bias vg vm 1/n bias (2/n) x v0 (1/n) x v0
ST7669V ver 1.3 16/208 6/4/2008 6.3 system control name i/o description cls i reserved for testing only. please fix this pin to vdd. cl i/o reserved for testing only. leave this pin op en. csel i this pin should connect to vdd. tcap i/o test pin. please let it open. vref o for monitor reference voltage only. please let it open. vpp i when writing otp, it needs outer power supply vo ltage 7.5~7.75v (>4ma) input to write successfully. 6.4 microprocessor interface name i/o description /rst i reset input pin. when rst is l, and initiali zation is executed. if[3:1] i parallel / serial data input select input if3 if2 if1 mpu interface type h h h 80 series 16-bit parallel h h l 80 series 8-bit parallel h l h 68 series 16-bit parallel h l l 68 series 8-bit parallel l h h 8-bit serial (4 line) l h l 9-bit serial (3 line) l l h 80 series 18-bit parallel l l l 68 series 18-bit parallel note: 1. when fixing if2=h & if1=l, if3 can be defined as parallel/serial selection pin. if3=h: parallel interface (80 8-bit); if3=l: seria l interface (3-line) 2. refer to table 7.1-1.for detail interface connec tion. /cs i chip select input pin. data / instruction i/o is enabled only when /cs is " l". when chip select is non-active, d0 to d17 become high impedance. a0 i register select input pin a0 = "h": d0 to d17 or si are display data a0 = "l": d0 to d17 or si are control data ** in 3-line/4-line interface this pad will be used for scl function
ST7669V ver 1.3 17/208 6/4/2008 rw_wr i read / write execution control pin. (this pin is on ly used in parallel interface) mpu type rw_wr description 6800-series rw read / write control input pin rw = h : read rw = l : write 8080-series /wr write enable clock input pin. the data on d0 to d17 are latched at the rising edge of the /wr signal. when in the serial interface, connect it to vdd. e_rd i read / write execution control pin. (this pin is on ly used in parallel interface) mpu type e_rd description 6800-series e read / write control input pin rw= h: if e is h, d0 to d17 are in an output sta tus. rw = l: the data on d0 to d17 are latched at the falling edge of the e signal. 8080-series /rd read enable clock input pin when /rd is l, d0 to d17 are in an output status. when in the serial interface, connect it to vdd. d17 to d0 i/o they connect to the standard 8-bit or 16 bit mpu bus via the 8/16/18 Cbit bi-directional bus. when the following interface is selected and the /c s pin is high, the following pins become high impedance. 1. in 8-bit parallel: d17-d8 pins are in the state of high impedance should connect to vdd. 2. in 3-line/4-line interface d0 pad will be used f or si function 3. in 4-line interface d1 pad will be used for a0 fu nction 4. in serial interface: no-used pins are in the stat e of high impedance should connect to vdd. si i si is used to input serial data when the serial inte rface is selected.(3 line and 4 line) in ST7669V, d0 is the si when select serial interface . see table 7.1.1 scl i scl is used to input serial clock when the serial in terface is selected. the data is converted in the rising edge. (3 line a nd 4 line) in ST7669V, a0 is the scl when select serial interface . see table 7.1.1 te o tearing effect output. /ext i otp burn-in control pin. when burning otp, please add an external vss on /ext. there is a pull-high resistor between /ext & vdd in st76 69v. when using normal instruction table, please let it open. when using extension instruction table, please conn ect /ext to vss. note 1. in any status the control bus and data bus cant be floating. 2. the no-used pins should connect to vdd (supply dig ital voltage)
ST7669V ver 1.3 18/208 6/4/2008 6.5 lcd driver outputs name i/o description seg0 to seg395 o lcd segment driver outputs the display data and the m signal control the outpu t voltage of segment driver. segment driver output voltage display data m (internal) normal display reverse display h h vg vss h l vss vg l h vss vg l l vg vss sleep-in mode vss vss com0 to com161 o lcd common driver outputs the internal scanning data and m signal control the output voltage of common driver. scan data m (internal) common driver output voltage h h xv0 h l v0 l h vm l l vm sleep-in mode vss name i/o description tgi tgo i o tgi must connect to tgo by ito which run a ring on lcm glass trui truo i o trui must connect to truo by ito tlui tluo i o tlui must connect to tluo by ito trbi trbo i o trbi must connect to trbo by ito tlbi tlbo i o tlbi must connect to tlbo by ito
ST7669V ver 1.3 19/208 6/4/2008 driving waveform figure 6.5-1 ST7669V com/seg driving waveform ST7669V i/o pin ito resister limitation pin name ito resister vdd, vdd2~vdd5, vss,vss1,vss2,vss4 <100 v0 in , v0 out , v0 s ,xv0 in , xv0 out ,xv0 s , vg in , vg out ,vg s ,vm <300 vpp <50 a0, e_rd, rw_wr, /cs, d0 d17, (si), (scl), te <1k /rst <10k if[3:1], cls, csel, /ext <1k tcap, cl, vref floating note: 1. make sure that the ito resistance of com0 ~ com161 is equal, and so is it of seg0 ~ seg395. these limitations include the bottleneck of ito layout. 2. the ito layout suggestion is shown as below: figure 6.5-2 power ito layout suggestion
ST7669V ver 1.3 20/208 6/4/2008 7 functional description 7.1 microprocessor interface chip select input /cs pin is for chip selection. the ST7669V is active when /cs=l. in serial interface mode, the internal s hift register and the counter are reset when /cs=h. 7.1.1 selecting parallel / serial interface ST7669V has eight types of interface with an mpu, whi ch are two serial and six parallel interfaces. this parallel or serial interface is determined by if pin as shown in table 7.1-1. table 7.1-1parallel / serial interface mode i/f mode pin assignment if3 if2 if1 i/f description /cs a0 e_rd rw_wr used data bus d1 d0 h h l 80 serial 8-bit parallel /cs a0 /rd /wr d7~d2 d1 d0 h h h 80 serial 16-bit parallel /cs a0 /rd /wr d15~d2 d1 d0 l l h 80 serial 18-bit parallel /cs a0 /rd /wr d17~d2 d1 d0 h l l 68 serial 8-bit parallel /cs a0 e r/w d7~d2 d1 d0 h l h 68 serial 16-bit parallel /cs a0 e r/w d15~d2 d1 d0 l l l 68 serial 18-bit parallel /cs a0 e r/w d17~d2 d1 d0 l h h 8-bit spi mode (4 line) /cs scl -- -- -- a0 si l h l 9-bit spi mode (3 line) /cs scl -- -- -- --- si note: when these pins are set to any other combinati on, a0, e_rd and rw_wr inputs are disabled and d0 to d17 are to be high impedance. 7.1.2 8-bit or 16-bit parallel interface the ST7669V identifies the type of the data bus sign als according to the combination of a0, /rd (e) and /wr (w/r) signals, as shown in table 7.1-2. table 7.1-2parallel data transfer common 6800-series 8080-series a0 r/w e /rd /wr description h h h display data read out h h h register status read l l h instruction write h l h display data write
ST7669V ver 1.3 21/208 6/4/2008 figure 7.1-1 parallel data transfer example chart relation between data bus and gradation data ST7669V offers 256 color display, 4096 color display , 65k color display, and 262k color display. when usi ng 256 colors, 4096, 65k, and 262k display; you can specify color fo r each of r, g, and b using the palette function. us e the command for switching between these modes. (1) 256 color input mode 1. 8-bit interface d7, d6, d5, d4, d3, d2, d1, d0: rrr ggg bb 1st -write there is only 1 write operation for 1 pixel data. 1 pixel data is written in the display data ram when 1st -write operation finishes. (2) 4096-color display (1-1) type a 4096 color display 1. 8-bit mode d7, d6, d5, d4, d3, d2, d1, d0: rrrr gggg 1st-write d7, d6, d5, d4, d3, d2, d1, d0: bbbb rrrr 2nd-write d7, d6, d5, d4, d3, d2, d1, d0: gggg bbbb 3rd-write there are 3 write operations for 2 pixel data. 1st pixel data is written in the display data ram wh en 2nd Cwrite operation finishes, and 2nd pixel dat a is written in the
ST7669V ver 1.3 22/208 6/4/2008 display data ram when 3rdCwrite operation finishes. 2. 16-bit mode d15, d14, d13, d12, d11, d10, d9, d8, d7, d6, d5, d 4, d3, d2, d1, d0: rrrr gggg bbbb xxxx 1st-write there is only 1 write operation for 1 pixel data. 1 pixel data is written in the display data ram when 1st Cwrite operation finishes. x are ignored dum my bits. (3) 65k color input mode 1. 8-bit mode d7, d6, d5, d4, d3, d2, d1, d0: rrrrr ggg 1st-write d7, d6, d5, d4, d3, d2, d1, d0: ggg bbbbb 2nd-write there are 2 write operations for 1 pixel data. 1st pixel data is written in the display data ram wh en 2nd Cwrite operation finishes. 2. 16-bit mode d15, d14, d13, d12, d11, d10, d9, d8, d7, d6, d5, d 4, d3, d2, d1, d0: rrrrr gggggg bbbbb there is only 1 write operation for 1 pixel data. 1 pixel data is written in the display data ram when 1st Cwrite operation finishes. (4) 262k color input mode 1. 8-bit mode d7, d6, d5, d4, d3, d2, d1, d0: rrrrrr xx 1st-write d7, d6, d5, d4, d3, d2, d1, d0: gggggg xx 2nd-write d7, d6, d5, d4, d3, d2, d1, d0: bbbbbb xx 3rd-write there are 3 write operations for 1 pixel data. 1st pixel data is written in the display data ram wh en 3rdCwrite operation finishes. x are ignored du mmy bits. 2. 16 bit mode d15, d14, d13, d12, d11, d10, d9, d8, d7, d6, d5, d 4, d3, d2, d1, d0: rrrrrr xx gggggg xx 1st-write d15, d14, d13, d12, d11, d10, d9, d8, d7, d6, d5, d 4, d3, d2, d1, d0: bbbbbb xxxxxxxxxxxx 2nd-write there are 2 write operations for 1 pixel data. 1st pixel data is written in the display data ram wh en 2nd Cwrite operation finishes. x are ignored d ummy bits. 3. 18 bit mode d17, d16, d15, d14, d13, d12, d11, d10, d9, d8, d7, d6, d5, d4, d3, d2, d1, d0: rrrrrr gggggg bbbbbb there is only 1 write operation for 1 pixel data. 1 pixel data is written in the display data ram when 1st Cwrite operation finishes. x are ignored dum my bits.
ST7669V ver 1.3 23/208 6/4/2008 7.1.3 8- and 9-bit serial interface the 8-bit serial interface uses four pins /cs, si, scl , and a0 to enter commands and data. meanwhile, the 9-bit serial interface uses three pins /cs, si and scl for the same purpose. data read is not available in the serial interface. data entered must be 8 bits. the relation between gray-scale data and data bus in the serial input is the same as that in the 8-bit parallel interface mode at every gradati on. (1) 8-bit serial interface (4-line) when entering data (parameters): a0= high at the ris ing edge of the 8 th scl. when entering command: a0= low at the rising edge o f the 8 th scl
ST7669V ver 1.3 24/208 6/4/2008 when entering reading command: (2) 9-bit serial interface (3-line) when entering data (parameters): si= high at the ris ing edge of the 1 st scl. when entering command: si= low at the rising edge of the 1 st scl. when entering reading command : if /cs is set to high while the 8 bits from d7 to d 0 are entered, the data concerned is invalidated. be fore entering succeeding sets of data, you must correctly input t he data concerned again. in order to avoid data transfer error due to incom ing noise, it is recommended to set /cs at high on b yte basis to initialize the serial-to-parallel conversion counte r and the register.
ST7669V ver 1.3 25/208 6/4/2008 7.1.4 8-bit and 9-bit serial interface data color c oding 8-bit serial interface (4-line) (1) r 3-bit, g 3-bit, b 2-bit, 256 colors there is 1 pixel ( = 3 sub-pixels ) per byte. (2) r 4-bit, g 4-bit, b 4-bit, 4,096 colors type a there are 2 pixel ( = 3 sub-pixels ) per 3 byte.
ST7669V ver 1.3 26/208 6/4/2008 (4) r 5-bit, g 6-bit, b 5-bit, 65,536 colors there is 1 pixel ( = 3 sub-pixels ) per 2 byte. (5) r 6-bit, g 6-bit, b 6-bit, 262,144 colors there is 1 pixel ( = 3 sub-pixels ) per 3 byte.
ST7669V ver 1.3 27/208 6/4/2008 9-bit serial interface (3-line) (1) r 3-bit, g 3-bit, b 2-bit, 256 colors there is 1 pixel ( = 3 sub-pixels ) per byte. (2) r 4-bit, g 4-bit, b 4-bit, 4,096 colors C type a there are 2 pixel ( = 3 sub-pixels ) per 3 byte.
ST7669V ver 1.3 28/208 6/4/2008 (4) r 5-bit, g 6-bit, b 5-bit, 65,536 colors there is 1 pixel ( = 3 sub-pixels ) per 2 byte. (5) r 6-bit, g 6-bit, b 6-bit, 262,144 colors there is 1 pixel ( = 3 sub-pixels ) per 3 byte.
ST7669V ver 1.3 29/208 6/4/2008 7.2 access to ddram and internal registers ST7669V realizes high-speed data transfer because th e access from mpu is a sort of pipeline processing d one via the bus holder attached to the internal, requiring the cycl e time alone without needing the wait time. for example, when mpu writes data to the ddram, the d ata is once held by the bus holder and then written to the ddram before the succeeding write cycle is started. when mpu reads data from the ddram, the first read cycle is dummy and the bus holder holds the data read in the dummy cycle, and then it read from the bus holder to the system bus in the succeeding read cycle. figure 7.2-1 illustrates these relations. in 80-series interface mode: n dummy d (n ) d (n +1) mpusignal a0 data internalsignals addresscounter /rd n d (n ) d (n +1) d (n +2) d (n +3) internallatch read operation /wr /wr /rd d (n ) d (n +1) d (n +2) figure 7.2-1
ST7669V ver 1.3 30/208 6/4/2008 7.3 display data ram (ddram) 7.3.1 ddram it is 132 x 162 x 18 bits capacity ram prepared for storing dot data. refer to the following memory map for the ram configuration. memory map rgb alignment data control command column 0 1 131 (madctr) mx=0 131 130 0 (madctr) mx=1 color r g b r g b r g b data page (madctr) my=0 (madctr) my=1 0 161 1 160 2 159 3 158 4 157 5 156 6 155 7 154 : : 154 7 155 6 156 5 157 4 158 3 159 2 160 1 161 0 segout 0 1 2 3 4 5 393 394 395 you can change position of r and b with madctr comman d.
ST7669V ver 1.3 31/208 6/4/2008 7.3.2 address control the address counter sets the addresses of the displ ay data ram for writing. data is written pixel into the ram matrix of ST7669V . the data for one pixel or two pixels is collected (rgb 6-6-6 bit), according to the data formats. as soon as this pixel -data information is complete, the write access i s activated on the ram. the locations of ram are addressed by the addre ss pointers. the address ranges are x=0 to x=131 (8 3h) and y=0 to y=161 (a1h). addresses outside these ranges are no t allowed. before writing to the ram, a window must be defined i nto which will be written. the window is programmab le via the command registers xs, ys designating the start addr ess and xe, ye designating the end address. for example the whole display contents will be writ ten, the window is defined by the following values: xs=0 (0h) ys=0 (0h) and xe=131 (83h), ye=161 (a1h). in vertical addressing mode (mv=1), the y-address in crements after each byte, after the last y-address (y=ye), y wraps around to ys and x increments to address the next c olumn. in horizontal addressing mode (mv=0), the x-a ddress increments after each byte, after the last x-addres s (x=xe), x wraps around to sc and y increments to a ddress the next row. after the every last address (x=xe and y=xe) the address pointers wrap around to address (x=xs and y =ys). for flexibility in handling a wide variety of display a rchitectures, the commands caset, raset and madctr , define flags mx, my and mv, which allows mirroring of the x-addr ess and y-address. all combinations of flags are all owed. figure 7.3-1 show the available combinations of writing to the display ram. when mx, my and mv will be changed the data must be rewritten to the display ram. for each image condition, the controls for the colu mn and row counters apply as below: condition column counter row counter when ramwr command is accepted return to start column (xs) return to start row (ys) complete pixel read / write action increment by 1 no change the column counter value is larger than end column ( xe) return to start column (xs) increment by 1 the row counter value is larger than end row (ye) return to start column (xs) return to start row (ys)
ST7669V ver 1.3 32/208 6/4/2008 madctr parameter display data direction mv mx my image in the host (mpu) image in the driver (ddram) normal 0 0 0 y-mirror 0 0 1 x-mirror 0 1 0 x-mirror y-mirror 0 1 1 x-y exchange 1 0 0 x-y exchange y-mirror 1 0 1 x-y exchange x-mirror 1 1 0 x-y exchange x-mirror y-mirror 1 1 1 figure 7.3-1 frame data write direction according t o the madctr parameters (mv, mx and my)
ST7669V ver 1.3 33/208 6/4/2008 7.3.3 i/o buffer circuit it is the bi-directional buffer used when mpu reads or writes the ddram. since mpus read or write of ddram is performed independently from data output to the dis play data latch circuit, asynchronous access to the ddram when the lcd is turned on does not cause troubles such as fl icking of the display images. 7.3.4 scroll address circuit the circuit associates pages on ddram with com outp ut. ST7669V processes signals for the liquid crysta l display on 1-page basis. thus, when specifying a specific area in the area scroll display or partial display, you must designate it in block. 7.3.5 display data latch circuit this circuit is used to temporarily hold display da ta to be output from the ddram to the seg decoder circ uit. since display normal/inverse and display on/off commands are used to control data in the latch circuit alone, they d o not modify data in the ddram. 7.3.6 normal display on or partial mode on vertical scroll off in this mode, contents of the frame memory within a n area where column address is 00h to 83h and row a ddress is 00h to a1h is displayed. to display a dot on leftmost top corner, store the dot data at (column address, row address) = (0,0). example1) normal display on
ST7669V ver 1.3 34/208 6/4/2008 example2) partial display on: sr[15:0] = 0004h, er[15: 0] = 009eh, madctl (ml)=0 7.3.7 vertical scroll/rolling scroll rolling scroll there is just one types of vertical scrolling, whic h are determined by the commands vertical scrolling definition (33h) and vertical scrolling start address (37h). figure 7.3-2 rolling scroll definition when vertical scrolling definition parameters (tfa+vsa+bfa) =162. in this case, rolling scrolling is applied as shown below. all the memory contents will be used.
ST7669V ver 1.3 35/208 6/4/2008 example1) panel size=132 x 162, tfa =3, vsa=157, bfa=2, ssa= 4, madctl (ml)=0: rolling scroll example2) panel size=132 x 162, tfa =2, vsa=157, bfa=3, ssa= 4, madctl (ml)=1: rolling scroll (tfa and bfa are exchanged) vertical scroll example there are 2 types of vertical scrolling, which are determined by the commands vertical scrolling defin ition (33h) and vertical scrolling start address (37h). case 1: tfa + vsa + bfa<162 n/a. do not set tfa + vsa + bfa<162. in that case, unexpec ted picture will be shown. case 2: tfa + vsa + bfa=162 (rolling scrolling)
ST7669V ver 1.3 36/208 6/4/2008 example1) when madctl parameter ml=0, tfa=0, vsa=162, bfa=0 and vscsad=40. example2) when madctl parameter ml=1, tfa=10, vsa=152 , bfa=0 and vscsad=30.
ST7669V ver 1.3 37/208 6/4/2008 7.3.8 tearing effect output line the tearing effect output line supplies to the mpu a panel synchronization signal. this signal can be ena bled or disabled by the tearing effect line off & on commands. the sig nal can be used by the mpu to synchronize frame memo ry writing when displaying video images. tearing effect line modes 1 stline 2 ndline 3 rdline 162thline te ( mode1) te ( mode2) t hdh t hcyc 20 line 142thline comscan internalsignal t hdh t vdh t vdh t cycle 142 line 162line 20 line 142 line 162 line frame frame1 frame2 mode 1 , the tearing effect output signal consists of v-sync (tvdh) information. it starts at 142 nd line signal and ends at the 162 nd line signal. there is one high pulse during each f rame. mode 2 , the tearing effect output signal consists of both h-sync(thdh) and v-sync(tvdh) information. te pin outpu t thdh pulse on each com scan signal. during 142 nd ~ 162 nd line signal, it output a high pulse which equals 1 thdh + 1 tvdh. note: during sleep in mode, the tearing effect output pin is active low.
ST7669V ver 1.3 38/208 6/4/2008 tearing effect line timing the tearing effect signal is described below: table 7.3-1ac characteristics of tearing effect sig nal idle mode off (frame rate = 77hz, n-line = 0x8c, vop=1 6.48v, vddi/vdda=1.8v/2.8v) symbol parameter min typ max unit description t vdl vertical timing low duration -- 11.4 12 ms t vdh vertical timing high duration 1 1.6 2 ms mode1 t hdl horizontal timing low duration -- 75 80 us t hdh horizontal timing high duration 3 5.17 5.5 us mode2 note: the timings in table 7.3-1 apply when madctr b4= 0 and b4=1 the signals rise and fall times (tf, tr) are stipu lated to be equal to or less than 15ns.
ST7669V ver 1.3 39/208 6/4/2008 example 1: mpu write is faster than panel read. data write to frame memory is now synchronized to t he panel scan. it should be written during the vertic al sync pulse of the tearing effect output line. this ensures that da ta is always written ahead of the panel scan and ea ch panel frame refresh has a complete new image:
ST7669V ver 1.3 40/208 6/4/2008 example 2: mpu write is slower than panel read. the mpu to frame memory write begins just after panel read has commenced i.e. after one horizontal sync pulse of the tearing effect output line. this allows time for the image to download behind the panel read pointer and finishing download during the subsequent frame before the rea d pointer catches the mpu to frame memory write po sition.
ST7669V ver 1.3 41/208 6/4/2008 7.4 gray-scale display ST7669V incorporates a 4frc & 31 pwm function circuit to display a 64 gray-scale display. 7.5 oscillation circuit ST7669V is built-in an oscillator circuit. it provide s internal clock without external resistor. this os cillator signal is used in the voltage converter and display timing generation circuit. 7.6 display timing generator circuit this circuit generates some signals to be used for displaying lcd. the display clock, which is generat ed by oscillation clock, generates the clock for the line counter and the signal for the display data latch. the line ad dress of on-chip ram is generated in synchronization with the display clock and the display data latch circuit latches the dis play data in synchronization with the display clock. the display data, which is read to the lcd driver, is complete ly independent of the access to the display data ram from the microproces sor. the display clock generates an lcd ac signal (m ), which enables the lcd driver to make an ac drive waveform, and also generates an internal common timing signa l and start signal to the common driver. the frame signal or th e line signal changes the m by setting internal ins truction. driving waveform and internal timing signal are shown in fi gure 7.3-3. fr(internal) m(internal) com0 com10 segn fosc 160 0 1 2 3 4 5 6 7 8 9 10 11 161 161 160 1 3 4 2 0 figure 7.3-3 2 frame ac driving waveform (duty rat io: 1/162)
ST7669V ver 1.3 42/208 6/4/2008 figure 7.3-4 n-line inversion driving waveform (n=1 0, duty ratio=1/162)
ST7669V ver 1.3 43/208 6/4/2008 7.7 power level definition 7.7.1 power on/off sequence during power off, if lcd is in the sleep out mode, vd d and vddi must be powered down minimum 200msec afte r /rst has been released. during power off, if lcd is in t he sleep in mode, vddi or vdda can be powered down mini mum 0msec after /rst has been released. /cs can be applied at any timing or can be permanent ly grounded. /rst has priority over /cs. there will be no damage to the display module if th e power sequences are not met. there will be no abnormal visible effects on the di splay panel during the power on/off sequences. there will be no abnormal visible effects on the di splay between end of power on sequence and before rec eiving sleep out command. also between receiving sleep in command and power off sequence. if /rst line is not held stable by host during power on sequence as defined in sections case1 and case2, then it will be necessary to apply a hardware reset (/rst) after hos t power on sequence is complete to ensure correct ope ration. otherwise function is not guaranteed. the power on/ off sequence is illustrated below: case 1 C /rst line is held high or unstable by host at power on if /rst line is held high or unstable by the host du ring power on, then a hardware reset must be applied after both vdda and vddi have been applied C otherwise correct funct ionality is not guaranteed. there is no timing rest riction upon this hardware reset. note: unless otherwise specified, timings herein sh ow cross point at 50% of signal/power level.
ST7669V ver 1.3 44/208 6/4/2008 case 2 C /rst line is held low by host at power on if /rst line is held low (and stable) by the host d uring power on, then the /rst must be held low for m inimum 10 sec after both vdd and vddi have been applied. note: unless otherwise specified, timings herein sh ow cross point at 50% of signal/power level. uncontrolled power off the uncontrolled power off means a situation when e .g. there is removed a battery without the controll ed power off sequence. there will not be any damages for the dis play module or the display module will not cause an y damages for the host or lines of the interface. at an uncontrolled power off the display will go blank and there will not be any visible effects within 1 second on the display (blank display) and remains blank until power on sequence powers it up.
ST7669V ver 1.3 45/208 6/4/2008 7.7.2 power levels 6 level modes are defined they are in order of maxi mum power consumption to minimum power consumption: 1. normal mode on (full display), idle mode off, sle ep out: in this mode, the display is able to show maximum 2 62k colors. 2. partial mode on, idle mode off, sleep out: in this mode part of the display is used with maxim um 262k colors. 3. normal mode on (full display), idle mode on, slee p out: in this mode, the full display area is used but wit h 8 colors. 4. partial mode on, idle mode on, sleep out: in this mode, part of the display is used but with 8 colors. 5. sleep in mode: in this mode, the dc:dc converter, internal oscilla tor and panel driver circuit are stopped. only the mcu interface and memory works with digital vddi power supply. content s of the memory are safe. 6. power off mode: in this mode, both analog vdda and digital vddi are rem oved. note: transition between modes 1-5 is controllable by mcu commands. mode 6 is entered only when both po wer supplies are removed.
ST7669V ver 1.3 46/208 6/4/2008 7.7.3 power flow chart for different power modes poweronsequence hwreset swreset sleepin normaldisplaymodeon idlemodeoff sleepin normaldisplaymodeon idlemodeon sleepin partialmodeon idlemodeoff sleepin partialmodeon idlemodeon sleepout normaldisplaymodeon idlemodeoff sleepout normaldisplaymodeon idlemodeon sleepout partialmodeon idlemodeoff sleepout partialmodeon idlemodeon normaldisplaymodeon=noron partialmodeon=ptlon idlemodeoff=idmoff idlemodeon=idmon sleepout=slpout sleepin=slpin noron ptlon slpin slpout slpin slpout slpin slpout slpin slpout ptlon noron noron ptlon ptlon noron idmon idmoff idmon idmoff idmon idmoff idmon idmoff sleepout sleepin note 1: there is not any abnormal visual effect when the re is changing from one power mode to another power mode. 2: there is not any limitation, which is not specif ied by this spec, when there is changing from one p ower mode to another power mode.
ST7669V ver 1.3 47/208 6/4/2008 7.8 liquid crystal driver power circuit the power supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. there are vo ltage converter circuits, voltage regulator circuit s, and voltage follower circuits. they are controlled by power con trol instruction. dc/dc booster block diagram
ST7669V ver 1.3 48/208 6/4/2008 7.8.1 voltage regulator circuits there is a built-in voltage regulator circuits in st 7669v for generating v0. after internal voltage is r egulated by voltage regulator circuit, v0 is generated. detail explanati on of v0 set is listed below: set v0 (temperature = 24 ) v0= 3.6 +{ vop[8:0] + vopoffset[6:0] + ( ev[6:0] -3fh)}x 0.04 (v) example1 (v0 setting>16.48v): vop[8:0]=1 01000010 (142h) vopoffset[6:0]=0000010 (02h) ev[6:0]=0111111 (3fh) v0=3.6 + {322 + 2 + (63-63) } x 0.04 =16.56 (v) example2 (v0 setting<16.48v): vop[8:0]= 1 01000010 (142h) vopoffset [6:0]=1000010 (42h) ev[6:0]=0111111 (3fh) v0=3.6 + {322 -62 + (63-63) } x 0.04 =14 (v) v0 restriction: because vg should larger than 1.8v, ST7669V v0 value sh ould be higher than 1.8 x bias / 2 (v) and lower than 18v . v0 value outside the available range is undefined. u sers has to ensure while selecting the temperature compensation that under all conditions and including all tolerances t hat the v0 voltage remains in the range. v0 setting min max 1/5 4.5 18.0 1/6 5.4 18.0 1/7 6.3 18.0 1/8 7.2 18.0 1/9 8.1 18.0 1/10 9.0 18.0 1/11 9.9 18.0 1/12 10.8 18.0 1/13 11.7 18.0 1/14 12.6 18.0 0 2 4 6 8 10 12 14 16 18 20 1/5 1/6 1/7 1/8 1/9 1/10 1/11 1/12 1/13 1/14 bias v0(voltage) inhibit v0 range available v0 range
ST7669V ver 1.3 49/208 6/4/2008 set v0 with temperature compensation (temperature 24 ) there are 16-line slope in each temperature steps a nd customer can select one line slope of temperatur e compensation coefficient for each temperature step. each temperature step is 8 o c. please s ee figure 7.3-5 as b elow. figure 7.3-5 in command tempset each mtx, where x=0, 1, 2,, e, f, h as a value between 0 and 15. mtx = 0 results in 0v increment on v0, mtx = 1 results in mx=5mv increment, , mtx = 15 results in mx=15x5mv=75mv increment. not e that each mtx individually corresponds to a temperature interval; the relations between mx and v0 quantity d ue to temperature v0(t) are described in the equations shown as follow s: temperature range equation v0(v) at temperature= t -40 Q t -32 v0(t) = v0(t24)+ (-32-t) m0 +( m1 + m2 + m3 + m4 + m5 + m6 + m7) 8 -32 Q t -24 v0(t) = v0(t24)+ (-24-t) m1 +( m2 + m3 + m4 + m5 + m6 + m7) 8 -24 Q t -16 v0(t) = v0(t24)+ (-16-t) m2 +( m3 + m4 + m5 + m6 + m7) 8 -16 Q t -8 v0(t) = v0(t24)+ (-8-t) m3 +( m4 + m5 + m6 + m7) 8 -8 Q t 0 v0(t) = v0(t24)+ (0-t) m4 +( m5 + m6 + m7) 8 0 Q t 8 v0(t) = v0(t24)+ (8-t) m5 +( m6 + m7) 8 8 Q t 16 v0(t) = v0(t24)+ (16-t) m6 + m7 8 16 Q t 24 v0(t) = v0(t24)+ (24-t) m7 24 Q t 32 v0(t) = v0(t24) (t-24) m8 32 Q t 40 v0(t) = v0(t24) (t-32) m9 m8 8 40 Q t 48 v0(t) = v0(t24) (t-40) m10 (m9 + m8 ) 8 48 Q t 56 v0(t) = v0(t24) (t-48) m11 (m10 + m9 + m8 ) 8 56 Q t 64 v0(t) = v0(t24) (t-56) m12 (m11 + m10 + m9 + m8 ) 8 64 Q t 72 v0(t) = v0(t24) (t-64) m13 (m12 + m11 + m10 + m9 + m8 ) 8 72 Q t 80 v0(t) = v0(t24) (t-72) m14 (m13 + m12 + m11 + m10 + m9 + m8 ) 8 80 Q t 88 v0(t) = v0(t24) (t-80) m15 ( m14 + m13 + m12 + m11 + m10 + m9 + m8 ) 8
ST7669V ver 1.3 50/208 6/4/2008
ST7669V ver 1.3 51/208 6/4/2008 the example of tc function (1) setting example for default tc curve command 0xf4 data 1 st : 0xcc 2 nd : 0x09 3 rd : 0x01 4 th : 0x01 5 th : 0x23 6 th : 0x41 7 th : 0x61 8 th : 0xf3 vop=16.48v bias=1/10 tc= -0.07% 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00 18.00 20.00 -30 -20 -10 0 10 20 30 40 50 60 70 80 temp. vop
ST7669V ver 1.3 52/208 6/4/2008 (2) setting example for -0.06%/ tc curve command 0xf4 data 1 st : 0x05 2 nd : 0x05 3 rd : 0x05 4 th : 0x05 5 th : 0x05 6 th : 0x05 7 th : 0x05 8 th : 0x05 vop=16.48v bias=1/10 tc= -0.06% 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00 18.00 20.00 -30 -20 -10 0 10 20 30 40 50 60 70 80 temp. vop
ST7669V ver 1.3 53/208 6/4/2008 (3) setting example for -0.11%/ tc curve command 0xf4 data 1 st : 0x09 2 nd : 0x09 3 rd : 0x09 4 th : 0x09 5 th : 0x09 6 th : 0x09 7 th : 0x09 8 th : 0x09 v0 fine tuning ST7669V has 2 commands for fine tuning v0. these comm ands are vopofsetinc (see section 9.1.50) and vopofsetdec (see section 9.1.51 ). when writing vopo fsetinc into ic for each time, v0 would increase 40 mv; when writing vopofsetdec into ic for each time, v0 would decrease 40mv. example: vop[8:0]=1 01000010 (142h) vopoffset[6:0]=0000010 (02h) ev[6:0]=0111111 (3fh) vopofsetinc x5 v0=3.6 + { 322 + 2 + (63-63) } x 0.04 + 0.04x5 = 16.76 (v) vop=16.48v bias=1/10 tc= -0.11% 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00 18.00 20.00 -30 -20 -10 0 10 20 30 40 50 60 70 80 temp. vop
ST7669V ver 1.3 54/208 6/4/2008 7.8.2 voltage follower circuits there is a build-in voltage follower circuits in st7 669v for generating vg and vm. these voltages are dec ided by bias ratio selection circuitry which is set by user s with software to control 1/5 to 1/14 bias ratios to match the optimum display performance of lcd panel. bias driving rule is listed below: lcd bias vg vm 1/n bias (2/n) x v0 (1/n) x v0 n=5 to 14 7.8.3 otp setting flow ST7669V provides the write and read function to writ e the electronic control value and built-in resista nce ratio into otp (one-time programming register), and then read them from it. using the write and read functions, y ou can store these values appropriate to each lcd panel. this fu nction is very convenient for user in setting from some different panels voltage. but using this function must attention the setting procedure. please see the following diagram . figure 7.3-6 otp programming flow note1: this setting flow is used for lcm assembler. note2: otp shouldnt be written without preceding l oading correctly from otp in order to avoid some errors during ic operation. note3: when writing value to otp, the voltage of vp p must be 7.5v~7.75v; the current of ivpp must be more than 4 ma. note4: if the otp is exposed to a high temperature for hours, data in the memory cell may probably be lost before the data retention guarantee period. to retain data in the memory cell, keep the memory ce ll below 90 . the data retention guarantee period is specified including the retention period.
ST7669V ver 1.3 55/208 6/4/2008 7.9 frequency temperature gradient compensation coe fficient 7.9.1 register loading detection ST7669V will auto-switch frame rate on different tem perature such as figure 7.3-7. ta, tb and tc are fram e rate switching temperatures which can be defined by cust omer with command tmprng. fa, fb, fc and fd are switch ed frame rate which also can be defined by customer wi th command frmsel. the frame rate range is from 18.75hz to 170hz. when the temperature is in increasing state, frame rate changes to the higher step at ta/tb/tc+th( ). whe n the temperature is in decreasing state, frame rate chan ges to the lower step at ta/tb/tc. for example: tc=10 and th=5 , fc switches to fd at 15 but fd switches to fc at 10 . please take figure 7.3-7 for reference. figure 7.3-7
ST7669V ver 1.3 56/208 6/4/2008 7.10 sleep out Ccommand and self-diagnostic functio ns of the display module 7.10.1 register loading detection sleep out-command is a trigger for an internal funct ion of the display module, which indicates, if the display module loading function of factory default values from otp rom (or similar device) to registers of the display control ler is working properly. there are compared factory values of the otp rom and register values of the display controller by the d isplay controller (1st step: compares register and otp rom values, 2nd step: loads otp rom values to registers). if those both values (otp rom and register values) are same, there is inv erted (= increased by 1) a bit, which is defined in command rddsdr) (the used bit of this command is d7). if tho se both values are not same, this bit (d7) is not i nverted (= not increased by 1). the flow chart for this internal function is follow ing:
ST7669V ver 1.3 57/208 6/4/2008 7.10.2 functionality detection sleep out-command is a trigger for an internal funct ion of the display module. the internal function (= the display controller) is comparing if the display module is still meeting f unctionality requirements (e.g. booster voltage levels, timings, etc.). if fu nctionality requirement is met, there is inverted ( = increased by 1) a bit, which defined in command read display self-diagnosti c result (0fh) (= rddsdr) (the used bit of this com mand is d6). if functionality requirement is not same, this bit (d6) is not inverted (= not increased by 1). the flow chart for this internal function is follow ing: note: there is needed 120msec after sleep out -comm and, when there is changing from sleep in Cmode to sleep out -mode, before there is possible to check if functionality requirements are met and a value o f rddsdrs d6 is valid. otherwise, there is 5msec delay for d6s value, when sleep out Ccommand is sent in sleep out -mode.
ST7669V ver 1.3 58/208 6/4/2008 7.10.3 chip attachment detection (reserved) sleep out-command is a trigger for an internal funct ion of the display module, which indicates, if bump side of ic is attached to lcm glass ito or not. there is inverted (= increased by 1) a bit, which i s defined in command read display self-diagnostic r esult (rddsdr). the used bit of this command is d5. if ic is not attached to the circuit route of the flex or display glass, this bit (d5) is not inverted (= not increased by 1). there are connected together 2 bumps via route of i to on 4 corners of ic. tlbi connects to tlbo; tlui co nnects to tluo; trui connects to truo; trbi connects to trbo. 7.10.4 lcm glass detection (reserved) sleep out-command is a trigger for an internal funct ion of the display module, which indicates, if the display glass of the display module is broken or not. there is inverted (= increased by 1) a bit, which i s defined in command read display self-diagnostic r esult (0fh) (= rddsdr).the used bit of this command is d4. if th is display glass is broken, this bit (d4) is not in verted (= not increased by 1). the following figure is a reference of how this gla ss break detection can be implemented. for example, there is connected together 2 bumps(tgi and tgo) via route o f ito. this route of ito is the nearest route of th e edge of the display glass . trui-truo tlui-tluo tlbi-tlbo trbi-trbo tgo tgi active area of the display glass
ST7669V ver 1.3 59/208 6/4/2008 8 reset circuit the registers that are initialized are listed below . item after power on after h ard ware reset after s oft ware reset frame memory (ram data) random no change no change rddid tbd tbd tbd rddpm 08h 08h 08h rddmadctr 00h 00h no change rddcolmod 06h (18 - bit/pixel) 06h (18 - bit/pixel) no change rddim 00h 00h 00h rddsm 00h 00h 00h rddsdr 00h 00h 00h sleep in/out in in in display mode (normal/partial) normal normal normal display inversion on/off off off off all p ixel off mode disable disable disable all pixel on mode disable disable disable contrast (ev) 3fh 3fh 3fh display on/off display off display off display off column: start address (xs) 00h 00h 00h column: end address (xe) 83h 83h 83h (when mv=0) a1h (when mv=1) row: start address (ys) 00h 00h 00h row: end address (ye) a1h a1h a1h (when mv=0) 83h (when mv=1) color set random random contents of the look-up table protected partial: start address (ps) 00h 00h 00h partial: end address (pe) a1h a1h a1h scroll: top fixed area (tfa) 00h 00h 00h scroll: scroll area (vsa) a2h a2h a2h scroll: bottom fixed area (bfa) 00h 00h 00h te on/off off off off te mode 0 (mode1) 0 (mode1) 0 (mode1) memory data access control my/mx/mv/ml/rgb) 00h 00h no change scroll start address (ssa) 00h 00h 00h idle mode on/off off off off interface color pixel format (p) 06h (18bit/pixel) 06h (18bit/pixel) no change id1 tbd tbd tbd id2 tbd tbd tbd id3 tbd tbd tbd drive duty a1 h a1 h a1 h first common 00h 00h 00h fosc divider no division no division no division common scan direction 0 1 61 0 1 61 0 1 61 vop 14 2h 14 2h 14 2h
ST7669V ver 1.3 60/208 6/4/2008 item after power on after h ard ware reset after s oft ware reset vop offset increase/decrease disable d isable d isable bias 1/ 1 0 bias 1/ 1 0 bias 1/ 1 0 bias booster setting 8 x 8 x 8 x booster efficiency 01 b 01 b 01 b vg source from vdd2 x2 from vdd2 x2 from vdd2 x2 epctin 0 0 0 o tp selection disable disable disable frame frequency in normal color (fa/fb/fc/fd) 46hz/61.5hz/72hz/77hz 46hz/61.5hz/72hz/77hz 46hz/61.5hz/72hz/77hz frame frequency in 8-color (idle) (f8a/f8b/f8c/f8d) 46hz/61.5hz/72hz/77hz 46hz/61.5hz/72hz/77hz 46hz/61.5hz/72hz/77hz temperature range (ta/tb/tc) -10 /0 /10 -10 /0 /10 -10 /0 /10 temperature hysteresis for fr 5 5 5 tempsel refer to 9.1.73 refer to 9.1.73 refer to 9.1.73 note. some of above default values can be modified by cust omer after otp writing. please refer to otp related register list related reg ister list for the content of otp.
ST7669V ver 1.3 61/208 6/4/2008 9 commands 9.1 instruction table command table-1 , /ext= h or l hex command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 function ref (00h) nop 0 1 0 0 0 0 0 0 0 0 0 no operation 9.1.1 (01h) swreset 0 1 0 0 0 0 0 0 0 0 1 software reset 9.1.2 (04h) rddid 0 1 0 0 0 0 0 0 1 0 0 read display id 9.1.3 - 1 0 1 - - - - - - - - dummy read - 1 0 1 id17 id16 id15 id14 id13 id12 id11 id10 id1 read (d23-d16) - 1 0 1 1 id26 id25 id24 id23 id22 id21 id20 id2 read (d15-d8) - 1 0 1 id37 id36 id35 id34 id33 id32 id31 id30 id3 read (d7-d0) (09h) rddst 0 1 0 0 0 0 0 1 0 0 1 read display status 9.1.4 - 1 0 1 - - - - - - - - dummy read - 1 0 1 st31 st30 st29 st28 st27 st26 st25 st24 (d31-d24) - 1 0 1 st23 st22 st21 st20 st19 st18 st17 st16 (d23-d16) - 1 0 1 st15 st14 st13 st12 st11 st10 st9 st8 (d15-d8) - 1 0 1 st7 st6 st5 st4 st3 st2 st1 st0 (d7-d0) (0ah) rddpm 0 1 0 0 0 0 0 1 0 1 0 read display power mode 9.1.5 - 1 0 1 - - - - - - - - dummy read - 1 0 1 d7 d6 d5 d4 d3 d2 0 0 - (0bh) rddmadctr 0 1 0 0 0 0 0 1 0 1 1 read display madctr 9.1.6 - 1 0 1 - - - - - - - - dummy read - 1 0 1 d7 d6 d5 d4 d3 0 0 0 - (0ch) rddcolmod 0 1 0 0 0 0 0 1 1 0 0 read display pixel format 9.1.7 - 1 0 1 - - - - - - - - dummy read - 1 0 1 0 0 0 0 0 d2 d1 d0 - (0dh) rddim 0 1 0 0 0 0 0 1 1 0 1 read display image mode 9.1.8 - 1 0 1 - - - - - - - - dummy read - 1 0 1 d7 0 d5 d4 d3 0 0 0 - (0eh) rddsm 0 1 0 0 0 0 0 1 1 1 0 read display signal mode 9.1.9 - 1 0 1 - - - - - - - - dummy read - 1 0 1 d7 d6 0 0 0 0 0 0 - (0fh) rddsdr 0 1 0 0 0 0 0 1 1 1 1 read display self-diagnostic result 9.1.10 - 1 0 1 - - - - - - - - dummy read 1 0 1 d7 d6 0 0 0 0 0 0 -
ST7669V ver 1.3 62/208 6/4/2008 hex command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 function ref (10h) slpin 0 1 0 0 0 0 1 0 0 0 0 sleep in & booster off 9.1.11 (11h) slpout 0 1 0 0 0 0 1 0 0 0 1 sleep out & booster on 9.1.12 (12h) ptlon 0 1 0 0 0 0 1 0 0 1 0 partial mode on 9.1.13 (13h) noron 0 1 0 0 0 0 1 0 0 1 1 partial off (normal) 9.1.14 (20h) invoff 0 1 0 0 0 1 0 0 0 0 0 display inversion off (normal) 9.1.15 (21h) invon 0 1 0 0 0 1 0 0 0 0 1 display inversion on 9.1.16 (22h) apoff 0 1 0 0 0 1 0 0 0 1 0 all pixel off (only for test purpose) 9.1.17 (23h) apon 0 1 0 0 0 1 0 0 0 1 1 all pixel on (only for test purpose) 9.1.18 (25h) wrcntr 0 1 0 0 0 1 0 0 1 0 1 write contrast 9.1.19 - 1 1 0 0 ev6 ev5 ev4 ev3 ev2 ev1 ev0 ev = 0 to 127 (28h) dispoff 0 1 0 0 0 1 0 1 0 0 0 display off 9.1.20 (29h) dispon 0 1 0 0 0 1 0 1 0 0 1 display on 9.1.21 (2ah) caset 0 1 0 0 0 1 0 1 0 1 0 column address set 9.1.22 1 1 0 xs15 xs14 xs13 xs12 xs11 xs10 xs9 xs8 x_adr start: 0 xs 83h Q Q 1 1 0 xs7 xs6 xs5 xs4 xs3 xs2 xs1 xs0 1 1 0 xe15 xe14 xe13 xe12 xe11 xe10 xe9 xe8 x_adr end: xs xe 83h Q Q 1 1 0 xe7 xe6 xe5 xe4 xe3 xe2 xe1 xe0 (2bh) raset 0 1 0 0 0 1 0 1 0 1 1 row address set 9.1.23 1 1 0 ys15 ys14 ys13 ys12 ys11 ys10 ys9 ys8 y_adr start: 0 ys a1h Q Q 1 1 0 ys7 ys6 ys5 ys4 ys3 ys2 ys1 ys0 1 1 0 ye15 ye14 ye13 ye12 ye11 ye10 ye9 ye8 y_adr end: ys ye a1h Q Q 1 1 0 ye7 ye6 ye5 ye4 ye3 ye2 ye1 ye0 (2ch) ramwr 0 1 0 0 0 1 0 1 1 0 0 memory write 9.1.24 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 write data (2eh) ramrd 0 1 0 0 0 1 0 1 1 1 0 memory read 9.1.25 1 1 0 - - - - - - - - 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 (30h) ptlar 0 1 0 0 0 1 1 0 0 0 0 partial start/end address set 9.1.26 - 1 1 0 ps15 ps14 ps13 ps12 ps11 ps10 ps9 ps8 start address (0~161) 1 1 0 ps7 ps6 ps5 ps4 ps3 ps2 ps1 ps0 1 1 0 pe15 pe14 pe13 pe12 pe11 pe10 pe9 pe8 end address (0~161) - 1 1 0 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0
ST7669V ver 1.3 63/208 6/4/2008 hex command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 function ref (33h) scrlar 0 1 0 0 0 1 1 0 0 1 1 scroll area 9.1.27 - 1 1 0 tfa7 tfa6 tfa5 tfa4 tfa3 tfa2 tfa1 tfa0 tfa=0~162 - 1 1 0 vsa7 vsa6 vsa5 vsa4 vsa3 vsa2 vsa1 vsa0 vsa=0~162 - 1 1 0 bfa7 bfa6 bfa5 bfa4 bfa3 bfa2 bfa1 bfa0 bfa=0~162 (34h) teoff 0 1 0 0 0 1 1 0 1 0 0 tearing effect line off 9.1.28 (35h) teon 0 1 0 0 0 1 1 0 1 0 1 tearing effect mode set & on 9.1.29 - 1 1 0 - - - - - - - m 0: mode1, 1: mode2 (36h) madctr 0 1 0 0 0 1 1 0 1 1 0 memory data access control 9.1.30 - 1 1 0 my mx mv ml rgb - - - - (37h) vscsad 0 1 0 0 0 1 1 0 1 1 1 scroll start address of ram 9.1.31 1 1 0 ssa7 ssa6 ssa5 ssa4 ssa3 ssa2 ssa1 ssa0 ssa = 0~161 (38h) idmoff 0 1 0 0 0 1 1 1 0 0 0 idle mode off 9.1.32 (39h) idmon 0 1 0 0 0 1 1 1 0 0 1 idle mode on 9.1.33 (3ah) colmod 0 1 0 0 0 1 1 1 0 1 0 interface pixel format 9.1.34 - 1 1 0 - - - - - p2 p1 p0 interface format (dah) rdid1 0 1 0 1 1 0 1 1 0 1 0 read id1 9.1.35 - 1 0 1 - - - - - - - - dummy read - 1 0 1 id17 id16 id15 id14 id13 id12 id11 id10 (d7-d0) (dbh) rdid2 0 1 0 1 1 0 1 1 0 1 0 read id2 9.1.36 - 1 0 1 - - - - - - - - dummy read - 1 0 1 id27 id26 id25 id24 id23 id22 id21 id20 (d7-d0) (dch) rdid3 0 1 0 1 1 0 1 1 0 1 0 read id3 9.1.37 - 1 0 1 - - - - - - - - dummy read - 1 0 1 id37 id36 id35 id34 id33 id32 id31 id30 (d7-d0) note 1: when /ext connects to h or floating, comman ds which are not defined in command table-1 are t reated as nop (00h) command. note 2: commands 10h, 12h, 13h, 20h, 21h, 25h, 28h, 29h, 30h, 36h (bit ml only), 38h and 39h are updat ed during v-sync when module is in sleep out mode to avoid abnormal visua l effects. during sleep in mode, these commands are updated im mediately. read status (09h), read display power mode (0ah), r ead display madctr (0bh), read display pixel format (0ch), read display image mode (0dh), read display signal mode (0eh) an d read display self diagnostic result (0fh) of thes e commands is updated immediately both in sleep in mode and sleep out mod e.
ST7669V ver 1.3 64/208 6/4/2008 command table-2 , /ext= l hex command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 function ref (b0h) dutyset 0 1 0 1 0 1 1 0 0 0 0 display duty setting 9.1.38 1 1 0 du7 du6 du5 du4 du3 du2 du1 du0 (b1h) firstcom 0 1 0 1 0 1 1 0 0 0 1 first com. page address 9.1.39 1 1 0 f7 f6 f5 f4 f3 f2 f1 f0 (b3h) oscdiv 0 1 0 1 0 1 1 0 0 1 1 fosc divider 9.1.40 1 1 0 - - - - - - cld1 cld0 (b4h) ptlmod 0 1 0 1 0 1 1 0 1 0 0 saving power mode selection 9.1.41 1 1 0 ptl m 0 0 1 1 0 0 0 (b5h) nlinvset 0 1 0 1 0 1 1 0 1 0 1 n-line control 9.1.42 1 1 0 m n6 n5 n4 n3 n2 n1 n0 (b7h) comscandir 0 1 0 1 0 1 1 0 1 1 1 com/seg scan direction for glass layout 9.1.43 1 1 0 0 smx 0 0 sbgr 0 0 1 (b8h) rmwin 0 1 0 1 0 1 1 1 0 0 0 read modify write control in 9.1.44 (b9h) rmwout 0 1 0 1 0 1 1 1 0 0 1 read modify write control out 9.1.45 (bbh) rdset 0 1 0 1 0 1 1 1 0 1 1 read data setting 9.1.46 1 1 0 0 0 1 0 0 1 1 0 (bch) idleimagesaving 0 1 0 1 0 1 1 1 1 0 0 idle image saving mode 9.1.47 1 1 0 0 0 0 0 idleim sunit 0 0 (bdh) dispcompstep 0 1 0 1 0 1 1 1 1 0 1 display compensation step 9.1.48 1 1 0 0 0 0 0 0 step2 step1 step0 (c0h) vopset 0 1 0 1 1 0 0 0 0 0 0 vop setting 9.1.49 1 1 0 vop7 vop6 vop5 vop4 vop3 vop2 vop1 vop0 1 1 0 - - - - - - - vop8 (c1h) vopofsetinc 0 1 0 1 1 0 0 0 0 0 1 +40mv/setp 9.1.50 (c2h) vopofsetdec 0 1 0 1 1 0 0 0 0 1 0 -40mv/setp 9.1.51 (c3h) biassel 0 1 0 1 1 0 0 0 0 1 1 bias selection 9.1.52 1 1 0 - - - - - bias2 bias1 bias0 (c4h) bstbmpxsel 0 1 0 1 1 0 0 0 1 0 0 booster setting 9.1.53 1 1 0 - - - - - bst2 bst 1 bst0
ST7669V ver 1.3 65/208 6/4/2008 hex command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 function ref (c5h) bsteffsel 0 1 0 1 1 0 0 0 1 0 1 booster efficiency selection 9.1.54 1 1 0 - - 1 0 - - btf1 btf0 (c7h) vopoffset 0 1 0 1 1 0 0 0 1 1 1 vop offset fuse bit adjust 9.1.55 1 1 0 0 vos6 vos5 vos4 vos3 vos2 vos1 vos0 (cbh) vgsorcsel 0 1 0 1 1 0 0 1 0 1 1 vg with booster x2 control 9.1.56 1 1 0 - - - - - - - 2bt0 (cch) id1set 0 1 0 1 1 0 0 1 1 0 0 id1 setting 9.1.57 1 1 0 id1_7 id1_6 id1_5 id1_4 id1_3 id1_2 id1_1 id1_0 (cdh) id2set 0 1 0 1 1 0 0 1 1 0 1 id2 setting 9.1.58 1 1 0 1 id2_6 id2_5 id2_4 id2_3 id2_2 id2_1 id2_0 (ceh) id3set 0 1 0 1 1 0 0 1 1 1 0 id3 setting 9.1.59 1 1 0 id3_7 id3_6 id3_5 id3_4 id3_3 id3_2 id3_1 id3_0 (d0h) anaset 0 1 0 1 1 0 0 0 0 0 0 analog circuit setting 9.1.60 1 1 0 0 0 0 1 1 1 0 1 (d7h) autoloadset 0 1 0 1 1 0 1 0 1 1 1 mask rom data auto re-load control 9.1.61 1 1 0 exte 1 - ard 1 1 1 1 (deh) rdtststatus 0 1 0 1 1 0 1 1 1 1 0 read ic status 9.1.62 1 0 1 - - - - - - - - dummy read (e0h) epctin 0 1 0 1 1 1 0 0 0 0 0 control otp wr/rd 9.1.63 1 1 0 0 0 wr /xrd 0 0 0 0 0 (e1h) epctout 0 1 0 1 1 1 0 0 0 0 1 otp control cancel 9.1.64 (e2h) epmwr 0 1 0 1 1 1 0 0 0 1 0 write to otp 9.1.65 (e3h) epmrd 0 1 0 1 1 1 0 0 0 1 1 read from otp 9.1.66 (e4h) otpsel 0 1 0 1 1 1 0 0 1 0 0 select otpb/otpc 9.1.67 1 1 0 ms1 ms0 0 1 1 0 0 0 (e5h) romset 0 1 0 0 1 1 1 0 1 0 1 programmable rom setting 9.1.68 1 1 0 0 0 0 0 1 1 1 0
ST7669V ver 1.3 66/208 6/4/2008 (f0h) frmsel 0 1 0 1 1 1 1 0 0 0 0 frame freq. in temp range a,b,c and d 9.1.69 1 1 0 - - - fa4 fa3 fa2 fa1 fa0 1 1 0 - - - fb4 fb3 fb2 fb1 fb0 1 1 0 - - - fc4 fc3 fc2 fc1 fc0 1 1 0 - - - fd4 fd3 fd2 fd1 fd0 (f1h) frm8sel 0 1 0 1 1 1 1 0 0 0 1 frame freq. in temp range a,b,c and d (idle) 9.1.70 1 1 0 - - - f8a4 f8a3 f8a2 f8a1 f8a0 1 1 0 - - - f8b4 f8b3 f8b2 f8b1 f8b0 1 1 0 - - - f8c4 f8c3 f8c2 f8c1 f8c0 1 1 0 - - - f8d4 f8d3 f8d2 f8d1 f8d0 (f2h) tmprng 0 1 0 1 1 1 1 0 0 1 0 temp range a,b and c 9.1.71 1 1 0 - ta6 ta5 ta4 ta3 ta2 ta1 ta0 1 1 0 - tb6 tb5 tb4 tb3 tb2 tb1 tb0 1 1 0 - tc6 tc5 tc4 tc3 tc2 tc1 tc0 (f3h) tmphys 0 1 0 1 1 1 1 0 0 1 1 hysteresis value set 9.1.72 1 1 0 - - - - th3 th2 th1 th0 (f4h) tempsel 0 1 0 1 1 1 1 0 1 0 0 tempsel 9.1.73 1 1 0 mt13 mt12 mt11 mt10 mt03 mt02 mt01 mt00 1 1 0 mt33 mt32 mt31 mt30 mt23 mt22 mt21 mt20 1 1 0 mt53 mt52 mt51 mt50 mt43 mt42 mt41 mt40 1 1 0 mt73 mt72 mt71 mt70 mt63 mt62 mt61 mt60 1 1 0 mt93 mt92 mt91 mt90 mt83 mt82 mt81 mt80 1 1 0 mtb3 mtb2 mtb1 mtb0 mta3 mta2 mta1 mta0 1 1 0 mtd3 mtd2 mtd1 mtd0 mtc3 mtc2 mtc1 mtc0 1 1 0 mtf3 mtf2 mtf1 mtf0 mte3 mte2 mte1 mte0 (f7h) thys 0 1 0 1 1 1 1 0 1 1 1 temperature detection threshold 9.1.74 1 1 0 thys7 thys6 thys5 thys4 thys3 thys2 thys1 thys0 (f9h) frame set 0 1 0 1 1 1 1 1 0 0 1 set frame rgb pwm 9.1.75 1 1 0 - - - p14 p13 p12 p11 p10 1 1 0 - - - p24 p23 p22 p21 p20 : : : : : : : : : : : 1 1 0 - - - p154 p153 p152 p151 p150 1 1 0 - - - p164 p163 p162 p161 p160
ST7669V ver 1.3 67/208 6/4/2008 9.1.1 nop: no operation (00h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 0 0 0 0 0 0 00h parameter no parameter description this command is an empty command; it does not have any effect on the display module. however it can be used to terminate frame memory wr ite or read as described in ramwr (memory write) and ramrd (memory read) comman ds. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence n/a s/w reset n/a h/w reset n/a flow chart
ST7669V ver 1.3 68/208 6/4/2008 9.1.2 swreset: software reset (01h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 0 0 0 0 0 1 01h parameter no parameter description when the software reset command is written, it cause s a software reset. it resets the commands and parameters to their s/w reset default values and all segment & common outputs are set to vm (display off: blank display). (see default tables in each com mand description) note: the frame memory contents are unaffected by t his command restriction it will be necessary to wait 5msec before sending n ew command following software reset. the display module loads all display suppliers fac tory default values to the registers during 5msec. if software reset is applied during sleep out mode, i t will be necessary to wait 120msec before sending sleep out command. software reset command cannot be sent during sleep ou t sequence. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence n/a s/w reset n/a h/w reset n/a
ST7669V ver 1.3 69/208 6/4/2008 flow chart
ST7669V ver 1.3 70/208 6/4/2008 9.1.3 rddidif: read display identification informat ion (04h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 0 0 0 1 0 0 04h dummy read 1 0 1 - - - - - - - - - 2 nd parameter 1 0 1 id17 id16 id15 id14 id13 id12 id11 id10 - 3 rd parameter 1 0 1 1 id26 id25 id24 id23 id22 id21 id20 - 4 th parameter 1 0 1 id37 id36 id35 id34 id33 id32 id31 id30 - note: - dont care description this read byte returns 24-bit display identificatio n information. 1st parameter: dummy read. the 2nd parameter (id17 to id10): lcd modules manu facturer id. the 3rd parameter (id26 to id20): lcd module/driver version id the 4th parameter (id37 to id30): lcd module/driver id. note: commands rdid1/2/3(dah, dbh, dch) read data corr espond to the parameters 2,3,4 of the command 04h, respectively. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status id1 id2 id3 power on sequence tbd tbd tbd s/w reset tbd tbd tbd h/w reset tbd tbd tbd
ST7669V ver 1.3 71/208 6/4/2008 flow chart
ST7669V ver 1.3 72/208 6/4/2008 9.1.4 rddst: read display status (09h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 0 0 1 0 0 1 09h dummy read 1 0 1 - - - - - - - - - 2 nd parameter 1 0 1 st31 st30 st29 st28 st27 st26 st25 st24 - 3 rd parameter 1 0 1 st23 st22 st21 st20 st19 st18 st17 st16 - 4 th parameter 1 0 1 st15 st14 st13 st12 st11 st10 st9 st8 - 5 th parameter 1 0 1 st7 st6 st5 st4 st3 st2 st1 st0 - note: - dont care description this command indicates the current status of the di splay as described in the table below: bit description value st31 booster voltage status 1=booster on (booster is ok) , 0=off st30 row address order (my) 1=decrement, 0=increment st29 column address order (mx) 1=decrement, 0=increment st28 row/column order (mv) 1= row/column exchange (mv=1) 0= normal (mv=0) st27 scan address order (ml) 1=decrement, 0=increment st26 rgb/bgr order (rgb) 1=bgr, 0=rgb st25 not used 0 st24 not used 0 st23 not used 0 st22 st21 st20 interface color pixel format definition 010 = not defined 011 = 12-bit / pixel type a 100 = not defined 101 = 16-bit / pixel, 110 = 18-bit / pixel, 111 = not defined st19 idle mode on/off 1 = on, 0 = off st18 partial mode on/off 1 = on, 0 = off st17 sleep in/out 1 = out, 0 = in st16 display normal mode on/off 1 = normal display on , 0 = normal display off st15 vertical scrolling status 1 = scroll on, 0 = scroll off st14 not used 0 st13 inversion status 1 = on, 0 = off st12 all pixels on 1 = mode on, 0 = mode off st11 all pixels off 1 = mode on, 0 = mode off st10 display on/off 1 = on, 0 = off st9 tearing effect line on/off 1 = on, 0 = off st8 not used 0 st7 not used 0 st6 not used 0 st5 tearing effect line mode 0 = mode1, 1 = mode2 st4 not used 0 st3 not used 0 st2 not used 0 st1 not used 0 st0 not used 0
ST7669V ver 1.3 73/208 6/4/2008 restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence 0000 0000_0101 0001_0000 0000_0000 0000 s/w reset 0xxx xx00_0xxx 0001_0000 0000_0000 0000 h/w reset 0000 0000_0101 0001_0000 0000_0000 0000 flow chart
ST7669V ver 1.3 74/208 6/4/2008 9.1.5 rddpm:read display power mode (0ah) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 0 0 1 0 1 0 0ah 1 st parameter 1 0 1 - - - - - - - - - 2 nd parameter 1 0 1 d7 d6 d5 d4 d3 d2 0 0 - note: - dont care description this command indicates the current status of the di splay as described in the table below: bit description value d7 booster voltage status 1=booster on, 0 =booster off d6 idle mode on/off 1 = idle mode on, 0 = idle mode off d5 partial mode on/off 1 = partial mode on, 0 = partial mode d4 sleep in/out 1 = sleep out, 0 = sleep in d3 display normal mode on/off 1 = normal display, 0 = par tial display d2 display on/off 1 = display on, 0 = display off d1 not used 0 d0 not used 0 restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (d7 to d0) power on sequence 0000_1000 (08h) s/w reset 0000_1000 (08h) h/w reset 0000_1000 (08h)
ST7669V ver 1.3 75/208 6/4/2008 flow chart
ST7669V ver 1.3 76/208 6/4/2008 9.1.6 rddmadctl: read display madctl (0bh) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 0 0 1 0 1 1 0bh 1 st parameter 1 0 1 - - - - - - - - - 2 nd parameter 1 0 1 d7 d6 d5 d4 d3 0 0 0 - note: - dont care description this command indicates the current status of the di splay as described in the table below: bit description value d7 row address order (my) 1=decrement, 0=increment d6 column address order (mx) 1=decrement, 0=increment d5 row/column order (mv) 1= row/column exchange (mv=1) 0= normal (mv=0) d4 scan address order (ml) 1=decrement, 0=increment d3 rgb/bgr order (rgb) 1=bgr, 0=rgb d2 not used 0 d1 not used 0 d0 not used 0 restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (d7 to d0) power on sequence 0000_0000 (00h) s/w reset no change h/w reset 0000_0000 (00h)
ST7669V ver 1.3 77/208 6/4/2008 flow chart
ST7669V ver 1.3 78/208 6/4/2008 9.1.7 rddcolmod: read display pixel format (0ch) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 0 0 1 1 0 0 0ch 1 st parameter 1 0 1 - - - - - - - - - 2 nd parameter 1 0 1 0 0 0 0 0 d2 d1 d0 - note: - dont care description this command indicates the current status of the di splay as described in the table below: bit descripti on value d7 0 (not used) d6 0 (not used) d5 0 (not used) d4 rgb interface color format 0 (not used) d3 0 d2 d1 d0 control interface color format 010=8 bit/pixel 011=12 bit/pixel (type a) 101=16 bit/pixel 110=18 bit/pixel the others = not defined restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (d7 to d0) power on sequence 18 bit/pixel s/w reset no change h/w reset 18 bit/pixel
ST7669V ver 1.3 79/208 6/4/2008 flow chart
ST7669V ver 1.3 80/208 6/4/2008 9.1.8 rddim: read display image mode (0dh) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 0 0 1 1 0 1 0dh 1 st parameter 1 0 1 - - - - - - - - - 2 nd parameter 1 0 1 d7 0 d5 d4 d3 0 0 0 - note: - dont care description this command indicates the current status of the di splay as described in the table below: bit description command 0 vertical scrolling off d7 vertical scrolling on/off 1 vertical scrolling is on, 0 inversion is off d5 inversion on/off 1 inversion is on 0 normal mode d4 all pixels on 1 all pixels are on 0 normal mode d3 all pixels off 1 all pixels are off restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (d7 to d0) power on sequence 0000_0000 (00h) s/w reset 0000_0000 (00h) h/w reset 0000_0000 (00h)
ST7669V ver 1.3 81/208 6/4/2008 flow chart
ST7669V ver 1.3 82/208 6/4/2008 9.1.9 rddsm: read display signal mode (0eh) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 0 0 1 1 1 0 0eh 1 st parameter 1 0 1 - - - - - - - - - 2 nd parameter 1 0 1 d7 d6 0 0 0 0 0 0 - note: - dont care descriptio n this command indicates the current status of the di splay as described in the table below: bit description command 0 tearing effect line off. d7 tearing effect line on/off 1 tearing effect on. 0 mode 1 d6 tearing effect line output mode 1 mode 2 d5 horizontal sync. (rgb i/f) on/off 0 (not used) d4 vertical sync. (rgb i/f) on/off 0 (not used) d3 pixel clock (dck, rgb i/f) on/off 0 (not used) d2 data enable (enable, rgb i/f) on/off 0 (not used) d1 not used 0 d0 not used 0 restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (d7 to d0) power on sequence 0000_0000 (00h) s/w reset 0000_0000 (00h) h/w reset 0000_0000 (00h)
ST7669V ver 1.3 83/208 6/4/2008 flow chart
ST7669V ver 1.3 84/208 6/4/2008 9.1.10 rddsdr: read display self-diagnostic result (0fh) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 0 0 1 1 1 1 0fh 1 st parameter 1 0 1 - - - - - - - - - 2 nd parameter 1 0 1 d7 d6 d5 d4 0 0 0 0 - note: - dont care description this command indicates the current status of the di splay as described in the table below: bit description command d7 register loading detection d6 functionality detection d5 chip attachment detection d4 lcm glass direction see section 7.10.1, 7.10.2, 7.10.3, 7.10.4 d3 not used 0 d2 not used 0 d1 not used 0 d0 not used 0 restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (d7 to d0) power on sequence 0000_0000 (00h) s/w reset 0000_0000 (00h) h/w reset 0000_0000 (00h) flow chart
ST7669V ver 1.3 85/208 6/4/2008 flow chart
ST7669V ver 1.3 86/208 6/4/2008 9.1.11 slpin : sleep in(10h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 0 1 0 0 0 0 10h parameter no parameter description this command causes the lcd module to enter the min imum power consumption mode. in this mode e.g. the dc/dc converter, internal osc illator, and panel scanning are all stopped. mcu interface and memory are still working and the memory keeps its contents. restriction this command has no effect when module is already i n sleep in mode. sleep in mode can only be left by the sleep out command (11h). it will be necessary to wait 5msec before sending next command, this is to allow time for the supply voltages and clock circuits to stabilize. it will be necessary to wait 120msec after sending sleep out command (when in sleep in mode) before sleep in command can be sent. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence sleep in mode s/w reset sleep in mode h/w reset sleep in mode flow chart it takes about 120 msec to get into sleep in mode ( booster off state) after slpin command issued. the results of booster off can be check by rddst (09 h) command bit31.
ST7669V ver 1.3 87/208 6/4/2008
ST7669V ver 1.3 88/208 6/4/2008 9.1.12 slpout: sleep out (11h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 0 1 0 0 0 1 11h parameter no parameter description this command turns off sleep mode. in this mode e.g . the dc/dc converter is enabled, internal oscillator is started, and panel scanning is starte d. restriction this command has no effect when module is already i n sleep out mode. sleep out mode can only be left by the sleep in command (10h). it will be necessary to wait 5msec before sending n ext command, this is to allow time for the supply voltages and clock circuits to stabilize. the display module loads all display suppliers fac tory default values to the registers during this 5m sec and there cannot be any abnormal visual effect on t he display image if factory default and register values are same when this load is done and when the display module is already sleep out Cmode. the display module is doing self-diagnostic functio ns during this 5msec. it will be necessary to wait 120msec after sending sleep in command (when in sleep out mode) before sleep out command can be sent. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence sleep in mode s/w reset sleep in mode h/w reset sleep in mode flow chart it takes 120msec to become sleep out mode (booster on mode) after slpout command issued. the results of booster on can be check by rddst (09h ) command bit31.
ST7669V ver 1.3 89/208 6/4/2008
ST7669V ver 1.3 90/208 6/4/2008 9.1.13 ptlon : partial mode on (12h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 0 1 0 0 1 0 12h parameter no parameter description this command turns on partial mode the partial mode window is described by the partial area command (30h). exit from ptlon by normal display mode on command (1 3h) there is no abnormal visual effect during mode chan ge between normal mode on <-> partial mode on. restriction this command has no effect when partial mode is acti ve. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence partial mode off s/w reset partial mode off h/w reset partial mode off flow chart see partial area (30h)
ST7669V ver 1.3 91/208 6/4/2008 9.1.14 noron: normal display mode on (13h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 0 1 0 0 1 1 13h parameter no parameter description this command returns the display to normal mode. normal display mode on means partial mode off. exit from noron by the partial mode on command (12h) there is no abnormal visual effect during mode chan ge between normal mode on <-> partial mode on. restriction this command has no effect when normal display mode is active. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence normal mode on s/w reset normal mode on h/w reset normal mode on flow chart see partial area and vertical scrolling definition descr iptions for details of when to use this command
ST7669V ver 1.3 92/208 6/4/2008 9.1.15 invoff: display inversion off (20h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 1 0 0 0 0 0 20h parameter no parameter description this command is used to recover from display invers ion mode. this command makes no change of contents of frame m emory. this command does not change any other status. restriction this command has no effect when ic is already in in version off mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence display inversion off s/w reset display inversion off h/w reset display inversion off
ST7669V ver 1.3 93/208 6/4/2008 flow chart
ST7669V ver 1.3 94/208 6/4/2008 9.1.16 invon: display inversion on (21h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 1 0 0 0 0 1 21h parameter no parameter description this command is used to enter into display inversio n mode. this command makes no change of contents of frame m emory. every bit is inverted from the frame memory to the display. this command does not change any other status. restriction this command has no effect when ic is already in in version on mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence display inversion off s/w reset display inversion off h/w reset display inversion off
ST7669V ver 1.3 95/208 6/4/2008 flow chart
ST7669V ver 1.3 96/208 6/4/2008 9.1.17 allpoff : all pixels off (22h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 1 0 0 0 1 0 22h parameter no parameter description this command is only used for test purposes e.g. pi xel response time (on/off) measurements on the passive matrix display. therefore, it is possible t hat this command is not used for final product soft ware. there is not used pwm or mixed frc/pwm driving meth od on the display. all driver outputs become low data state and displ ay becomes black. this command makes no change of contents of display memory. this command does not change any other status. exit commands are all pixels on, normal display m ode on and partial display on. the display is showing the contents of the frame me mory after normal display mode on and partial display on commands. restriction this command has no effect when ic is already in al l pixels off mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence all pixel off mode disable s/w reset all pixel off mode disable h/w reset all pixel off mode disable
ST7669V ver 1.3 97/208 6/4/2008 flow chart
ST7669V ver 1.3 98/208 6/4/2008 9.1.18 allpon: all pixels on (23h) (only for test p urposes) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 1 0 0 0 1 1 23h parameter no parameter description this command is only used for test purposes e.g. pi xel response time (on/off) measurements on the passive matrix display. therefore, it is possible t hat this command is not used for final product soft ware. there is not used pwm or mixed frc/pwm driving meth od on the display. all driver outputs become high data state and disp lay becomes white. this command makes no change of contents of display memory. this command does not change any other status. exit commands are all pixels on, normal display m ode on and partial display on. the display is showing the contents of the frame me mory after normal display mode on and partial display on commands. restriction this command has no effect when ic is already in al l pixels on mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence all pixel on mode disable s/w reset all pixel on mode disable h/w reset all pixel on mode disable
ST7669V ver 1.3 99/208 6/4/2008 flow chart
ST7669V ver 1.3 100/208 6/4/2008 9.1.19 wrcntr: write contrast (25h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 1 0 0 1 0 1 25h parameter 1 1 0 0 ev6 ev5 ev4 ev3 ev2 ev1 ev0 00h~7fh description this command is used to fine tuning the contrast of the current display. this contrast values can affect segment and common outputs. parameter range: 0-127dec. msb is ev6 and lsb is ev 0. default value: 63dec (3fh) restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence 3fh s/w reset 3fh h/w reset 3fh flow chart
ST7669V ver 1.3 101/208 6/4/2008 9.1.20 dispoff: display off (28h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 1 0 1 0 0 0 28h parameter no parameter description this command is used to enter into display off mode. in this mode, the output from frame memory is disabled and blank page inserted. this command makes no change of contents of frame m emory. this command does not change any other status. there will be no abnormal visible effect on the dis play. exit from this command by display on (29h) restriction this command has no effect when module is already i n display off mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence display off s/w reset display off h/w reset display off
ST7669V ver 1.3 102/208 6/4/2008 flow chart
ST7669V ver 1.3 103/208 6/4/2008 9.1.21 dispon: display on (29h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 1 0 1 0 0 1 29h parameter no parameter description turn on the display screen according to the current display data ram content and the display timing and setting. this command is used to recover from display off mode. output from the frame memory is enabled. this command makes no change of contents of frame m emory. this command does not change any other status. restriction this command has no effect when module is already i n display on mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence display off s/w reset display off h/w reset display off
ST7669V ver 1.3 104/208 6/4/2008 flow chart
ST7669V ver 1.3 105/208 6/4/2008 9.1.22 caset: column address set (2ah) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 1 0 1 0 1 0 2ah 1 st parameter 1 1 0 xs15 xs14 xs13 xs12 xs11 xs10 xs9 xs8 note1 2 nd parameter 1 1 0 xs7 xs6 xs5 xs4 xs3 xs2 xs1 xs0 note1 3 rd parameter 1 1 0 xe15 xe14 xe13 xe12 xe11 xe10 xe9 xe8 note1 4 th parameter 1 1 0 xe7 xe6 xe5 xe4 xe3 xe2 xe1 xe0 note1 description this command is used to define area of frame memory where mcu can access. this command makes no change on the other driver st atus. the values of xs[15:0] and xe[15:0] are referred whe n ramwr command comes. each value represents one column line in the frame memory. restriction xs[15:0] always must be equal to or less than xe[15:0 ] note 1: when xs[15:0] or xe[15:0] is greater than 8 3h (when madctls mv=0) or a1h (when madctls mv=1), data of out of range will be ignored register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status xs [15:0] xe [15:0] (mv=0) xe [15:0] (mv=1) power on sequence 00h 83h s/w reset 00h 83h a1h h/w reset 00h 83h
ST7669V ver 1.3 106/208 6/4/2008 flow chart
ST7669V ver 1.3 107/208 6/4/2008 9.1.23 raset: row address set (2bh) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 1 0 1 0 1 1 2bh 1 st parameter 1 1 0 ys15 ys14 ys13 ys12 ys11 ys10 ys9 ys8 note1 2 nd parameter 1 1 0 ys7 ys6 ys5 ys4 ys3 ys2 ys1 ys0 note1 3 rd parameter 1 1 0 ye15 ye14 ye13 ye12 ye11 ye10 ye9 ye8 note1 4 th parameter 1 1 0 ye7 ye6 ye5 ye4 ye3 ye2 ye1 ye0 note1 description this command is used to define area of frame memory where mcu can access. this command makes no change on the other driver st atus. the values of ys[15:0] and ye[15:0] are referred when ramwr command comes. each value represents one page line in the frame memory. restriction ys[15:0] always must be equal to or less than ye[15:0 ] note 1: when ys[15:0] or ye[15:0] are greater than a1h (when madctls mv=0) or 83h (when madctls mv=1), data of out of range will be ignored . register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status ys [15:0] ye [15:0] (mv=0) ye [15:0] (mv=1) power on sequence 00h a1h s/w reset 00h a1h 83h h/w reset 00h a1h
ST7669V ver 1.3 108/208 6/4/2008 flow chart
ST7669V ver 1.3 109/208 6/4/2008 9.1.24 ramwr: memory write (2ch) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 1 0 1 1 0 0 2ch write d1[7:0] 1 1 0 d17 d16 d15 d14 d13 d12 d11 d10 00h ~ ffh 1 1 0 dx7 dx6 dx5 dx4 dx3 dx2 dx1 dx0 00h ~ ffh write dn[7:0] 1 1 0 dn7 dn6 dn5 dn4 dn3 dn2 dn1 dn0 00h ~ ffh description this command is used to transfer data from mcu to f rame memory. this command makes no change to the other driver s tatus. when this command is accepted, the column register and the page register are reset to the start column/start page positions. the start column/start row positions are different i n accordance with madctr setting. then d[7:0] is stored in frame memory and the colum n register and the row register incremented as in section 7.3. frame write can be canceled by sending any other co mmand. restriction in all color modes, there is no restriction on leng th of parameters. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence contents of memory is set randomly s/w reset contents of memory is remained h/w reset contents of memory is remained
ST7669V ver 1.3 110/208 6/4/2008 flow chart
ST7669V ver 1.3 111/208 6/4/2008 9.1.25 ramro : memory read (2eh) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 1 0 1 1 1 0 2eh 1 st parameter 1 0 1 x x x x x x x x x 2 nd parameter 1 0 1 d17 d16 d15 d14 d13 d12 d11 d10 00h ~ ffh 1 0 1 dx7 dx6 dx5 dx4 dx3 dx2 dx1 dx0 00h ~ ffh (n+1)th parameter 1 0 1 dn7 dn6 dn5 dn4 dn3 dn2 dn1 dn0 00h ~ ffh description this command is used to transfer data from frame me mory to mcu. this command makes no change to the other driver st atus. when this command is accepted, the column register and the page register are reset to the start column/start page positions. the start column/start page positions are different i n accordance with madctl setting. (see 7.3) then d[7:0] is read back from the frame memory and the column register and the page register incremented as in section 7.3 frame read can be stopped by sending any other comm and. restriction in all color modes, the frame read is always 18bit so there is no restriction on length of parameters. note C memory read is only possible via the parallel interface. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence contents of memory is set randomly s/w reset contents of memory is not cleared h/w reset contents of memory is not cleared
ST7669V ver 1.3 112/208 6/4/2008 flow chart
ST7669V ver 1.3 113/208 6/4/2008 9.1.26 ptlar: partial area (30h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 1 1 0 0 0 0 30h 1 st parameter 1 1 0 ps15 ps14 ps13 ps12 ps11 ps10 ps9 ps8 2 nd parameter 1 1 0 ps7 ps6 ps5 ps4 ps3 ps2 ps1 ps0 00h ~ a1h 3 rd parameter 1 1 0 pe15 pe14 pe13 pe12 pe11 pe10 pe9 pe8 4 th parameter 1 1 0 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 00h ~ a1h description this command defines the partial modes display are a. there are 2 parameters associated with this command, the first defines the start line (ps) and the second the end line (pe), as illustrated in the figures below. ps and pe refer to the frame m emory line counter. if end line > start line when madctr ml=0: if end line > start line when madctr ml=1: if end line < start line when madctr ml=0: * row1: frame memory row address 1. if end line = start line then the partial area will be one line deep. restriction ps[15:0] and pe[15:0] cannot be greater than a1h.
ST7669V ver 1.3 114/208 6/4/2008 register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence ps[15:0]=0000h pe[15:0]=00a1h s/w reset ps[15:0]=0000h pe[15:0]=00a1h h/w reset ps[15:0]=0000h pe[15:0]=00a1h flow chart 1. to enter partial mode: pltar sr[15:0] er[15:0] ptlon partial mode
ST7669V ver 1.3 115/208 6/4/2008 9.1.27 rlar: scroll area (33h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex scrlar 0 1 0 0 0 1 1 0 0 1 1 (33h) 1 st parameter 1 1 0 tfa7 tfa6 tfa5 tfa4 tfa3 tfa2 tfa1 tfa0 - 2 nd parameter 1 1 0 vsa7 vsa6 vsa5 vsa4 vsa3 vsa2 vsa1 vsa0 - 3 rd parameter 1 1 0 bfa7 bfa6 bfa5 bfa4 bfa3 bfa2 bfa1 bfa0 - description this command just defines the vertical scrolling area of the display and not performs vertical scroll. when madctl ml=0 the 1st parameter tfa [7:0] describes the top fixed area (in no. of lines from top of the frame memory and display). the 2nd parameter vsa [7:0] describes the height of t he vertical scrolling area (in no. of lines of the frame memory [not the display] from the vertical scro lling start address) the first line appears immediately after the bottom most line of the top f ixed area. the 3rd parameter bfa [7:0] describes the bottom fixed area (in no. of lines from bottom of the frame memory and display). tfa, vsa and bfa refer to the frame memory line pointer. restriction the condition is (tfa+vsa+bfa) = 162, otherwise scrolling mode is undefined. in vertical scroll mode, madctl parameter mv should be set to 0-this only affects the frame memory write.tfa[7:0], vsa[7:0] and bfa[7:0] are based on line u nit. tfa[7:0]= 00h, 01h, 02h, 03h, , a1h vsa[7:0]= 00h, 01h, 02h, 03h, , a1h bfa[7:0]= 00h, 01h, 02h, 03h, , a1h register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes
ST7669V ver 1.3 116/208 6/4/2008 default default value status tfa [7:0] vsa [7:0] bfa [7:0] power on sequence 00h a2h 00h s/w reset 00h a2h 00h h/w reset 00h a2h 00h flow chart note: the frame memory window size must be defined correctly otherwise undesirable image will be displ ayed.
ST7669V ver 1.3 117/208 6/4/2008 flow chart note: scroll mode can be exit by both the normal di splay mode on(13h) and partial mode on (12h) comman ds.
ST7669V ver 1.3 118/208 6/4/2008 9.1.28 teoff: tearing effect line off (34h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 1 1 0 1 0 0 34h parameter no parameter description this command is used to turn off (active low) the te aring effect output signal from the te signal line. restriction this command has no effect when tearing effect outpu t is already off. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence tearing effect off s/w reset tearing effect off h/w reset tearing effect off flow chart
ST7669V ver 1.3 119/208 6/4/2008 9.1.29 teon: tearing effect line on (35h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 1 1 0 1 0 1 35h 1 st parameter 1 1 0 - - - - - - - m - note: - dont care description this command is used to turn on the tearing effect output signal from the te signal line. this output i s not affected by changing madctl bit ml. the tearing effect line on has one parameter, which describes the mode of the tearing effect output line. (-=dont care). when m=0: the tearing effect output signal consists of v-sync(t vdh) information. when m=1: the tearing effect output signal consists of both h- sync(thdh) and v-sync(tvdh) information. note: during sleep in mode with tearing effect line on, tearing effect output pin will be active low. restriction this command has no effect when tearing effect outpu t is already on. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence tearing effect off & m=0 s/w reset tearing effect off & m=0 h/w reset tearing effect off & m=0
ST7669V ver 1.3 120/208 6/4/2008 flow chart
ST7669V ver 1.3 121/208 6/4/2008 9.1.30 madctl: memory access control (36h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 1 1 0 1 1 0 36h 1 st parameter 1 1 0 my mx mv ml rgb - - - - note: - dont care description this command defines read/write scanning direction of frame memory. this command makes no change on the other driver st atus. note: ml affects to partial area (30h), vertical scrol ling definition (33h), vertical scrolling start addre ss (37h), partial on (12h) commands bit name description mx page address order my column address order mv page/column selection these 3 bits controls mcu to memory write/read direction. ml vertical order lcd vertical refresh direction con trol rgb rgb-bgr order color selector switch control (0=rgb color filter panel, 1=bgr color filter panel) the contents of the frame memory are not changed. ml:line(scan) address order note: top-left (0,0) means a physical memory locati on. restriction
ST7669V ver 1.3 122/208 6/4/2008 register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence my=0,mx=0,ml=0,rgb=0 s/w reset no change h/w reset my=0,mx=0,ml=0,rgb=0 flow chart
ST7669V ver 1.3 123/208 6/4/2008 9.1.31 scsad: vertical scroll start address of ram (37h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex vscsad 0 1 0 0 0 1 1 0 1 1 1 (37h) parameter 1 1 0 ssa7 ssa6 ssa5 ssa4 ssa3 ssa2 ssa1 ssa0 description this command is used together with verti cal scrolling definition (33h). these two commands describe the scrolling area and the scrolling mode. the vertical scrolling start address command has one parameter which describes which line in the frame memory will be written as the first line afte r the last line of the top fixed area on the display as illustrated below: this command start the scrolling. exit from v-scrolling mode by commands partial mode on (12h) or normal mode on (13h). when madctl ml=0 example: when top fixed area=bottom fixed area=00, vertical scrol ling area=162 and vertical scrolling pointer ssa=3. when madctl ml=1 example: when top fixed area=bottom fixed area=00, vertical scrol ling area=162 and vertical scrolling pointer ssa=3. note: when new pointer position and picture data are sent, the result on the display will happen at the next panel scan to avoid tearing effect. ssa refers to the frame memory line pointer.
ST7669V ver 1.3 124/208 6/4/2008 restriction since the value of the vertical scrolling start address is absolute (with reference to the fra me memory), it must not enter the fixed area (defined by vertical scrolling definition (33h)-otherwise undesirable image will be displayed on the panel. ssa [7:0] is based on line unit. ssa [7:0] = 00h, 01h, 02h, 03h, , a1h register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out no partial mode on, idle mode on, sleep out no sleep in yes default status default value power on sequence 00h s/w reset 00h h/w reset 00h flow chart see vertical scrolling definition (33h) des cription.
ST7669V ver 1.3 125/208 6/4/2008 9.1.32 idmoff: idle mode off (38h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 1 1 1 0 0 0 38h parameter no parameter description this command is used to recover from idle mode on. there will be no abnormal visible effect on the dis play mode change transition. in the idle off mode, 1. lcd can display maximum 262,144 colors. 2. normal frame frequency is applied. restriction this command has no effect when module is already i n idle off mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence idle off mode s/w reset idle off mode h/w reset idle off mode flow chart
ST7669V ver 1.3 126/208 6/4/2008 9.1.33 idmon: idle mode on (39h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 1 1 1 0 0 1 39h parameter no parameter description this command is used to enter into idle mode on. there will be no abnormal visible effect on the dis play mode change transition. in the idle on mode, 1. color expression is reduced. the primary and the secondary colors using msb of each r, g and b in the frame memory, 8 color depth data i s displayed. 2. 8-color mode frame frequency is applied. 3. exit from idmon by idle mode off (38h) command memory contents v.s display color r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 black 0xxxxx 0xxxxx 0xxxxx blue 0xxxxx 0xxxxx 1xxxxx red 1xxxxx 0xxxxx 0xxxxx magenta 1xxxxx 0xxxxx 1xxxxx green 0xxxxx 1xxxxx 0xxxxx cyan 0xxxxx 1xxxxx 1xxxxx yellow 1xxxxx 1xxxxx 0xxxxx white 1xxxxx 1xxxxx 1xxxxx x=don't care restriction this command has no effect when module is already i n idle on mode.
ST7669V ver 1.3 127/208 6/4/2008 register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence idle off mode s/w reset idle off mode h/w reset idle off mode flow chart
ST7669V ver 1.3 128/208 6/4/2008 9.1.34 colmod: interface pixel format (3ah) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 0 0 1 1 1 0 1 0 3ah 1 st parameter 1 1 0 - - - - - d2 d1 d0 - note: - dont care description this command is used to define the format of rgb pic ture data, which is transferred via the mcu interface. the formats are shown in the table: interface format d2 d1 d0 not defined 0 0 0 not defined 0 0 1 8 bit/pixel 0 1 0 12 bit/pixel(type a) 0 1 1 not defined 1 0 0 16 bit/pixel 1 0 1 18 bit/pixel 1 1 0 not defined 1 1 1 note: in 8 bit/pixel or 16 bit/pixel mode, the lut is applied to transfer data into the frame memory. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence 06h (18bit/pixel) s/w reset no change h/w reset 06h (18bit/pixel)
ST7669V ver 1.3 129/208 6/4/2008 flow chart 16 bit/pixel mode colmod 011 12 bit/pixel mode
ST7669V ver 1.3 130/208 6/4/2008 9.1.35 rdid1: read id1 (dah) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 1 1 0 1 1 0 1 0 dah 1 st parameter 1 0 1 - - - - - - - - - 2 nd parameter 1 0 1 id17 id16 id15 id14 id13 id12 id11 id10 - note: - dont care description this read byte returns 8-bit lcd modules manufactu rer id d7-d0 (id17 to id10): lcd modules manufacturer id. note: see command rddid (04h), 2nd parameter. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence tbd s/w reset tbd h/w reset tbd flow chart
ST7669V ver 1.3 131/208 6/4/2008 9.1.36 rdid2: read id2 (dbh) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 1 1 0 1 1 0 1 1 dbh 1 st parameter 1 0 1 x - - - - - - - - 2 nd parameter 1 0 1 1 id26 id25 id24 id23 id22 id21 id20 - note: - dont care description this read byte returns 8-bit lcd module/driver vers ion id d7-d0 (id27 to id20): lcd module/driver version id parameter range: id=80h to ffh note: see command rddid (04h), 3rd parameter. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence tbd s/w reset tbd h/w reset tbd flow chart
ST7669V ver 1.3 132/208 6/4/2008 9.1.37 rdid3: read id3 (dch) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 1 1 0 1 1 1 0 0 dch 1 st parameter 1 0 1 - - - - - - - - - 2 nd parameter 1 0 1 id37 id36 id35 id34 id33 id32 id31 id30 - note: - dont care description this read byte returns 8-bit lcd module/driver id. d7-d0 (id37 to id30): lcd module/driver id. note: see command rddid (04h), 4th parameter. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence tbd s/w reset tbd h/w reset tbd flow chart
ST7669V ver 1.3 133/208 6/4/2008 9.1.38 dutyset: display duty setting (b0h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex dutyset 0 1 0 1 0 1 1 0 0 0 0 (b0h) parameter 1 1 0 du7 du6 du5 du4 du3 du2 du1 du0 - description this command is used to set display duty. command s et = display duty numbers - 1. example: duty du7 du6 du5 du4 du3 du2 du1 du0 command set= display duty numbers-1 example: 1/162 duty 1 0 1 0 0 0 0 1 162-1=161 restriction display duty must > 4 (1/4 duty) register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (du[7:0]) power on sequence 10100001b (a1h) s/w reset 10100001b (a1h) h/w reset 10100001b (a1h) flow chart
ST7669V ver 1.3 134/208 6/4/2008 9.1.39 firstcom: first com. page address (b1h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex firstcom 0 1 0 1 0 1 1 0 0 0 1 (b1h) parameter 1 1 0 f7 f6 f5 f4 f3 f2 f1 f0 - description this command defines the first output com number th at mapping to the ram page address 0. for detail setting value, please see the table as below. f7 f6 f5 f4 f3 f2 f1 f0 line address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 2 : : : : : : : : : 1 0 1 0 1 1 1 0 160 1 0 1 0 1 1 1 1 161 example: if firstcom=8, common 8 would output the data of ram page address 0. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (f[7:0]) power on sequence 00h s/w reset 00h h/w reset 00h flow chart
ST7669V ver 1.3 135/208 6/4/2008 9.1.40 oscdiv: fosc divider (b3h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex oscdiv 0 1 0 1 0 1 1 0 0 1 1 (b3h) parameter 1 1 0 - - - - - - cld1 cld0 - note: - dont care description this command is used to specify the fosc dividing r atio. cld1, cld0: fosc dividing ratio. they are used to c hange number of dividing stages of internal clock. cld1 cld0 fosc dividing ratio 0 0 0 1 1 0 1 1 not divide 2 divisions 4 divisions 8 divisions restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (cld[0:1]) power on sequence 00b s/w reset 00b h/w reset 00b flow chart
ST7669V ver 1.3 136/208 6/4/2008 9.1.41 ptlmod: partial saving power mode selection (b4h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex oscdiv 0 1 0 1 0 1 1 0 1 0 0 (b4h) parameter 1 1 0 ptlm 0 0 1 1 0 0 0 - description two type partial modes are built in ST7669V. one is normal mode(ptlm=0) and another is power saving mode(ptml=1). when entering power saving mod e, ic would change bias, v0, booster pumping times special partial lines in orde r to save power consumptions. the detail content is showed as below: duty bias bst pump v0(v) 24 1/7 5x 8.64 32 1/7 5x 9.40 40 1/7 5x 9.92 48 1/9 6x 11.64 restriction the power saving power mode is customized. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence 18h s/w reset 18h h/w reset 18h flow chart
ST7669V ver 1.3 137/208 6/4/2008 9.1.42 nlinvset: n-line control (b5h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex nlinvset 0 1 0 1 0 1 1 0 1 0 1 (b5h) parameter 1 1 0 m n6 n5 n4 n3 n2 n1 n0 - description this command is used to set the inverted line numbe r with range of 2 to (duty-1) to improve display quality. when m=0, inversion occurs in every frame; when m=1, inversion is independent from frames. if n[6:0]=0, n-line inversion function is d isable. line inversion numbers=n[6:0] +1. example: if n[6:0]=7, inversion occurs per 8 line. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status m n[6:0] power on sequence 0b 0000000b s/w reset 0b 0000000b h/w reset 0b 0000000b flow chart
ST7669V ver 1.3 138/208 6/4/2008 9.1.43 comscandir: com/seg scan direction for glass layout(b7h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex comscandir 0 1 0 1 0 1 1 0 1 1 1 (b7h) parameter 1 1 0 0 smx 0 0 sbgr 0 0 1 - description it is used to specify the common output direction i n the pin of csel = l. this command helps to improve common ito layout tolerance on the lcm. when csel=l configuration is selected, pins and commo n outputs are scanned in the order shown below. function 0 1 smx inverse the mx setting inverse mx keep mx sbgr inverse the bgr setting keep bgr inverse bgr restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence 49h s/w reset 49h h/w reset 49h flow chart
ST7669V ver 1.3 139/208 6/4/2008 9.1.44 rmwin: read modify write control in (b8h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex rmwin 0 1 0 1 0 1 1 1 0 0 0 (b8h) parameter no parameter description read modify write control in restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence -- s/w reset -- h/w reset --
ST7669V ver 1.3 140/208 6/4/2008 9.1.45 rmwout: read modify write control out(b9h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex rmwout 0 1 0 1 0 1 1 1 0 0 1 (b9h) parameter no parameter description read modify write control out restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence -- s/w reset -- h/w reset --
ST7669V ver 1.3 141/208 6/4/2008 9.1.46 rdset: read data setting(bbh) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex rmwout 0 1 0 1 0 1 1 1 0 1 1 (bbh) parameter 1 1 0 0 0 1 0 0 1 1 0 - description read display data setting control restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence 26h s/w reset 26h h/w reset 26h
ST7669V ver 1.3 142/208 6/4/2008 9.1.47 idleimagesaving: idle image saving mode(bch) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex rmwout 0 1 0 1 0 1 1 1 1 0 0 (bch) parameter 1 1 0 0 0 0 0 idleim sunit 0 0 - description idleim: idle image (white/black image) saving mode setting. sunit: display compensation step unit setting. function 0 1 idleim white/black saving setting n-line normal n-line off sunit display compensation unit mode1 mode2 restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence 0ch s/w reset 0ch h/w reset 0ch
ST7669V ver 1.3 143/208 6/4/2008 9.1.48 dispcompstep: display compensation step(bdh) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex rmwout 0 1 0 1 0 1 1 1 1 0 1 (bdh) parameter 1 1 0 0 0 0 0 0 step2 step1 step0 - description the command is used to program the optimum lcd displa y quality. restriction step2 step1 step0 step 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence 02h s/w reset 02h h/w reset 02h
ST7669V ver 1.3 144/208 6/4/2008 9.1.49 vopset: vop set (c0h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex vopset 0 1 0 1 1 0 0 0 0 0 0 (c0h) 1 st parameter 1 1 0 vop7 vop6 vop5 vop4 vop3 vop2 vop1 vop0 - 2 nd parameter 1 1 0 - - - - - - - vop8 note: - dont care description the command is used to program the optimum lcd supply voltage v0. restriction the range of vop[8:0] is from 96 to 511. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (vop=16.48v) vop8 vop[7:0] power on sequence 1 01000010b (42h) s/w reset 1 01000010b (42h) h/w reset 1 01000010b (42h) flow chart
ST7669V ver 1.3 145/208 6/4/2008 9.1.50 vopofsetinc: vop increase 1 (c1h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex vopofsetinc 0 1 0 1 1 0 0 0 0 0 1 (c1h) description with the vopofsetinc and vopofsetdec command the v lcd voltage and therewith the contrast of the lcd can be adjusted. this command increases the value of vop offset regi ster by 1. if you set the electronic control value to 1111111, the control value is set to 0000000 after this command has been executed. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence -- s/w reset -- h/w reset -- flow chart
ST7669V ver 1.3 146/208 6/4/2008 9.1.51 vopofsetdec: vop decrease 1 (c2h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex vopofsetdec 0 1 0 1 1 0 0 0 0 1 0 (c2h) description with the vopofsetinc and vopofsetdec command the v lcd voltage and therewith the contrast of the lcd can be adjusted. this command decreases the value of vop offset reg ister by 1. if you set the electronic control value to 0000000, the control value is set to 1111111 after this command has been executed. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence -- s/w reset -- h/w reset -- flow chart
ST7669V ver 1.3 147/208 6/4/2008 9.1.52 biassel: bias selection(c3h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex biassel 0 1 0 1 1 0 0 0 0 1 1 (c3h) parameter 1 1 0 - - - - - bias2 bias1 bias0 - note: - dont care description select lcd bias ratio of the voltage required for dr iving the lcd. bais2 bais1 bais0 lcd bias 0 0 0 1/14 0 0 1 1/13 0 1 0 1/12 0 1 1 1/11 1 0 0 1/10 1 0 1 1/9 1 1 0 1/7 1 1 1 1/5 restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (bias[2:0]) power on sequence 100b s/w reset 100b h/w reset 100b flow chart
ST7669V ver 1.3 148/208 6/4/2008 9.1.53 bstpmpxsel: booster set(c4h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex bstpmpxsel 0 1 0 1 1 0 0 0 1 0 0 (c4h) parameter 1 1 0 - - - - - bst2 bst 1 bst0 - note: - dont care description booster setting bst2 bst1 bst0 0 0 0 x1 boosting circuit (booster off) 0 0 1 x2 boosting circuit 0 1 0 x3 boosting circuit 0 1 1 x4 boosting circuit 1 0 0 x5 boosting circuit 1 0 1 x6 boosting circuit 1 1 0 x7 boosting circuit 1 1 1 x8 boosting circuit restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (bst[2:0]) power on sequence 111b s/w reset 111b h/w reset 111b
ST7669V ver 1.3 149/208 6/4/2008 flow chart
ST7669V ver 1.3 150/208 6/4/2008 9.1.54 bsteffsel: booster efficiency selection(c5h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex bsteffsel 0 1 0 1 1 0 0 0 1 0 1 (c5h) parameter 1 1 0 - - 1 0 - - btf1 btf0 - note: - dont care description booster efficiency set btf1 btf0 frequency ( hz ) 0 0 level 1 0 1 level 2 (default) 1 0 level 3 by booster stages (2x, 3x, 4x, 5x, 6x, 7x, 8x) and boos ter efficiency (level1~3) commands, we could easily set the best booster performance with s uitable current consumption. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (btf[1:0]) power on sequence 01b s/w reset 01b h/w reset 01b flow chart
ST7669V ver 1.3 151/208 6/4/2008 9.1.55 vopoffset: vop offset fuse bit adjust(c7h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex vopoffset 0 1 0 1 1 0 0 0 1 1 1 (c7h) parameter 1 1 0 - vos6 vos5 vos4 vos3 vos2 vos1 vos0 - note: - dont care description the command is used to the vop offset for v0. for v os[6:0] setting, please see the following table: vos[6] vos[5:0] (dec) v0 offset 111111 63 +2520 mv 111110 62 +2480 mv 111101 61 +2440 mv 000010 2 +80 mv 000001 1 +40 mv 0 000000 0 0 mv 111111 -1 -40 mv 111110 -2 -80 mv 000010 -61 -2440 mv 000001 -62 -2480 mv 1 000000 -63 -2520 mv restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value vos6 vos[5:0] power on sequence 0 0 s/w reset 0 0 h/w reset 0 0
ST7669V ver 1.3 152/208 6/4/2008 flow chart
ST7669V ver 1.3 153/208 6/4/2008 9.1.56 v3sorcsel: fv3 with bst2x control(cbh) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex v3sorcsel 0 1 0 1 1 0 0 1 0 1 1 (cbh) parameter 1 1 0 - - - - - - - 2bt0 - note: - dont care description 2bt0=0: vg source comes from vdd2 ; 2bt0=1: vg source comes from 2-times charge pump. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (2bt0) power on sequence 1 s/w reset 1 h/w reset 1 flow chart
ST7669V ver 1.3 154/208 6/4/2008 9.1.57 id1set : id1 setting(cch) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex id1set 0 1 0 1 1 0 0 1 1 0 0 (cch) parameter 1 1 0 id1_7 id1_6 id1_5 id1_4 id1_3 id1_2 id1_1 id1_0 - description id1 setting for otpb program data input restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence tbd s/w reset tbd h/w reset tbd flow chart
ST7669V ver 1.3 155/208 6/4/2008 9.1.58 id2set : id2 setting(cdh) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex id2set 0 1 0 1 1 0 0 1 1 0 1 (cdh) parameter 1 1 0 1 id2_6 id2_5 id2_4 id2_3 id2_2 id2_1 id2_0 - description id2 setting for otpc program data input restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence tbd s/w reset tbd h/w reset tbd flow chart
ST7669V ver 1.3 156/208 6/4/2008 9.1.59 id3set : id3 setting(ceh) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex id3set 0 1 0 1 1 0 0 1 1 1 0 (ceh) parameter 1 1 0 id3_7 id3_6 id3_5 id3_4 id3_3 id3_2 id3_1 id3_0 - description id3 setting for optb program data input restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence tbd s/w reset tbd h/w reset tbd flow chart
ST7669V ver 1.3 157/208 6/4/2008 9.1.60 anaset: analog circuit setting(d0h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex autoloadset 0 1 0 1 1 0 1 0 0 0 0 (d0h) parameter 1 1 0 0 0 0 1 1 1 0 1 - description analog circuit setting. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value d[7:0] power on sequence 1dh s/w reset 1dh h/w reset 1dh flow chart
ST7669V ver 1.3 158/208 6/4/2008 9.1.61 autoloadset : mask rom data auto re-load con trol(d7h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex autoloadset 0 1 0 1 1 0 1 0 1 1 1 (d7h) parameter 1 1 0 exte otpbe - ard - - - - - note: - dont care description mask rom data auto re-load control exte : external command enable (otpc bit), 1: enable, 0: disable otpbe: otpb auto-read enable (otpc bit), 1: enable, 0: dis able. ard: otpb/otpc auto read enable control, 1: disable otpb/ otpc auto read. 0: enable otpb/otpc auto read. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value exte ard power on sequence 0 0 s/w reset 0 0 h/w reset 0 0 flow chart
ST7669V ver 1.3 159/208 6/4/2008 9.1.62 rdtststatus : read ic status(deh) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex rdtststatus 0 1 0 1 1 0 1 1 1 1 0 (deh) dummy read 1 0 1 - - - - - - - - parameter 1 0 1 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 - note: - dont care description read ic status. contact of otp / rda / pwr_vop read control . (selection byte by stusoutbytesel[3:0] control) restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence - s/w reset - h/w reset - flow chart
ST7669V ver 1.3 160/208 6/4/2008 9.1.63 epctin: control otp wr/rd(e0h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex epctin 0 1 0 1 1 1 0 0 0 0 0 (e0h) parameter 1 1 0 0 0 wr /xrd 0 0 0 0 0 - note: - dont care description wr/xrd: when setting 1 the write enable of otp will be opened. wr/xrd: when setting 0 the read enable of otp will be opened. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (wr/xrd) power on sequence 0 s/w reset 0 h/w reset 0 flow chart
ST7669V ver 1.3 161/208 6/4/2008 9.1.64 epcout: otp control cancel(e1h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex epcout 0 1 0 1 1 1 0 0 0 0 1 (e1h) note: - dont care description ic exits the otp control circuit when executing this command. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence -- s/w reset -- h/w reset -- flow chart
ST7669V ver 1.3 162/208 6/4/2008 9.1.65 epmwr: write to otp(e2h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex epcout 0 1 0 1 1 1 0 0 0 1 0 (e2h) note: - dont care description ic actives trigger to start otp programming when exe cuting this command. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence -- s/w reset -- h/w reset -- flow chart
ST7669V ver 1.3 163/208 6/4/2008 9.1.66 epmrd: read from otp(e3h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex epmrd 0 1 0 1 1 1 0 0 0 1 1 (e3h) note: - dont care description ic actives trigger to start otp data download to cir cuit when executing this command. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence s/w reset h/w reset flow chart
ST7669V ver 1.3 164/208 6/4/2008 9.1.67 otpsel: sel otp(e4h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex otpsel 0 1 0 1 1 1 0 0 1 0 0 (e4h) parameter 1 1 0 ms1 ms0 0 1 1 0 0 0 - note: - dont care description this command defines otp selection for eeprom control. please see the table as below: ms1 ms0 mode 0 0 disable 0 1 otpc 1 1 otpb restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (ms[1:0]) power on sequence 00 s/w reset 00 h/w reset 00
ST7669V ver 1.3 165/208 6/4/2008 flow chart
ST7669V ver 1.3 166/208 6/4/2008 9.1.68 romset: programmable rom setting(e5h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex autoloadset 0 1 0 0 1 1 1 0 1 0 1 (e5h) parameter 1 1 0 0 0 0 0 1 1 1 0 - note: - dont care description set the otp writing timing. value 0x0e is the best valu e for ST7669V. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value d[7:0] power on sequence 0fh s/w reset 0fh h/w reset 0fh flow chart
ST7669V ver 1.3 167/208 6/4/2008 9.1.69 frmsel: frame freq. in temp. range (f0h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 1 1 1 1 0 0 0 0 f0h 1 st parameter 1 1 0 - - - diva fa3 fa2 fa1 fa0 range a 2 nd parameter 1 1 0 - - - divb fb3 fb2 fb1 fb0 range b 3 rd parameter 1 1 0 - - - divc fc3 fc2 fc1 fc0 range c 4 th parameter 1 1 0 - - - divd fd3 fd2 fd1 fd0 range d description select frame freq. in normal display mode. 1 st parameter : frame freq. value set in temperature r ange 30(-30 ) to ta 2 nd parameter : frame freq. value set in temperature r ange ta to tb 3 rd parameter : frame freq. value set in temperature r ange tb to tc 4 th parameter : frame freq. value set in temperature r ange tc to 145(90 ) for command setting to frame rate value look-up-tab le, please see the following table: divx fx[3:0] frame rate(hz) tolerance: 10% divx fx[3:0] frame rate(hz) tolerance: 10% 0 75 0 18.75 1 76 1 27 2 77 2 37.5 3 80 3 40 4 84 4 42 5 88 5 44 6 92 6 46 7 97 7 48.5 8 102 8 51 9 108 9 54 a 115 a 57.5 b 123 b 61.5 c 133 c 66.5 d 144 d 72 e 155 e 77.5 1 f 170 0 f 85 restriction
ST7669V ver 1.3 168/208 6/4/2008 register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status fa[4:0] fb[4:0] fc[4:0] fd[4:0] power on sequence 06h 0bh 0dh 12h s/w reset 06h 0bh 0dh 12h h/w reset 06h 0bh 0dh 12h flow chart
ST7669V ver 1.3 169/208 6/4/2008 9.1.70 frm8sel: frame freq. in temp. range (idel-8 color) (f1h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 1 1 1 1 0 0 0 1 f1h 1 st parameter 1 1 0 - - - f8a4 f8a3 f8a2 f8a1 f8a0 range a 2 nd parameter 1 1 0 - - - f8b4 f8b3 f8b2 f8b1 f8b0 range b 3 rd parameter 1 1 0 - - - f8c4 f8c3 f8c2 f8c1 f8c0 range c 4 th parameter 1 1 0 - - - f8d4 f8d3 f8d2 f8d1 f8d0 range d description select frame freq. in normal display mode.(idle;8 co lor mode) 1 st parameter : frame freq. value set in temp range 30( -30 ) to ta 2 nd parameter : frame freq. value set in temp range ta to tb 3 rd parameter : frame freq. value set in temp range tb t o tc 4 th parameter : frame freq. value set in temp range tc to 145(90 ) restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status fa[4:0] fb[4:0] fc[4:0] fd[4:0] power on sequence 06h 0bh 0dh 12h s/w reset 06h 0bh 0dh 12h h/w reset 06h 0bh 0dh 12h
ST7669V ver 1.3 170/208 6/4/2008 flow chart 1st parameter. f8a[4:0] 2nd parameter. f8b[4:0] 3rd parameter. f8c[4:0] 4th parameter. f8d[4:0] frm8sl
ST7669V ver 1.3 171/208 6/4/2008 9.1.71 tmprng: temp. range set for frame freq. adj. (f2h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 1 1 1 1 0 0 1 0 f2h 1 st parameter 1 1 0 - ta6 ta5 ta4 ta3 ta2 ta1 ta0 range a 2 nd parameter 1 1 0 - tb6 tb5 tb4 tb3 tb2 tb1 tb0 range b 3 rd parameter 1 1 0 - tc6 tc5 tc4 tc3 tc2 tc1 tc0 range c description temperature range set for automatic frame freq. adj . operation according the current temperature value. 1 st parameter: temperature range a value set 2 nd parameter: temperature range b value set 3 rd parameter: temperature range c value set ta/tb/tc temperature( ) + 40 = ta/tb/tc[6:0] example: if ta wants to be set at 24 , ta[6:0]=24+40=64(40h), restriction -40 ta ta+th tb tb+th tc 87 Q Q Q Q Q Q register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status ta[6:0] tb[6:0] tc[6:0] power on sequence 1eh 28h 32h s/w reset 1eh 28h 32h h/w reset 1eh 28h 32h
ST7669V ver 1.3 172/208 6/4/2008 flow chart
ST7669V ver 1.3 173/208 6/4/2008 9.1.72 tmphys: temperature hysteresis set for frame freq. adj.(f3h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 1 1 1 1 0 0 1 1 f3h 1 st parameter 1 1 0 - - - - th3 th2 th1 th0 description temperature hysteresis range set for frame freq. adj. parameter th[3:0] is used to set temperature hysteresis range. the relationship between temperature state and temperature range value is shown below. temp range value temp rising state temp falling state freq. changing point a ta[6:0]+th[3:0] ta[6:0] freq. changing point b tb[6:0]+th[3:0] tb[6:0] freq. changing point c tc[6:0]+th[3:0] tc[6:0] th temperature( ) - 1 = th[3:0] example: if th wants to set 5 , th[3:0]=5 -1=4. restriction temperature hysteresis value should be smaller than the gap of temperature range. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value(th[3:0]) power on sequence 4h s/w reset 4h h/w reset 4h
ST7669V ver 1.3 174/208 6/4/2008 flow chart
ST7669V ver 1.3 175/208 6/4/2008 9.1.73 tempsel: temp. set(f4h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex tempsel 0 1 0 1 1 1 1 0 1 0 0 (f4h) 1 st parameter 1 1 0 mt13 mt12 mt11 mt10 mt03 mt02 mt01 mt00 mt1x : (-24 o c to -32 o c ) mt0x : (-32 o c to -40 o c ) 2 nd parameter 1 1 0 mt33 mt32 mt31 mt30 mt23 mt22 mt21 mt20 mt3x : (-8 o c to -16 o c ) mt2x : (-16 o c to -24 o c ) 3 rd parameter 1 1 0 mt53 mt52 mt51 mt50 mt43 mt42 mt41 mt40 mt5x : (8 o c to 0 o c ) mt4x : (0 o c to -8 o c ) 4 th parameter 1 1 0 mt73 mt72 mt71 mt70 mt63 mt62 mt61 mt60 mt7x : (24 o c to16 o c ) mt6x : (16 o c to 8 o c ) 5 th parameter 1 1 0 mt93 mt92 mt91 mt90 mt83 mt82 mt81 mt80 mt9x : (40 o c to 32 o c ) mt8x : (32 o c to 24 o c ) 6 th parameter 1 1 0 mtb3 mtb2 mtb1 mtb0 mta3 mta2 mta1 mta0 mtbx : (56 o c to 48 o c ) mtax : (48 o c to 40 o c ) 7 th parameter 1 1 0 mtd3 mtd2 mtd1 mtd0 mtc3 mtc2 mtc1 mtc0 mtdx : (72 o c to 64 o c ) mtcx : (64 o c to 56 o c ) 8 th parameter 1 1 0 mtf3 mtf2 mtf1 mtf0 mte3 mte2 mte1 mte0 mtfx : (87 o c to 80 o c ) mtex : (80 o c to 72 o c ) note: - dont care description this command defines temperature gradient compensat ion coefficient. for this command detail description and operation, please see sectio n 7.9. parameter n mt n 3 mt n 2 mt n 1 mt n 0 voltage / o c ( tolerance: 3mv/ o c ) 0 0 0 0 0 0 mv / o c 1 0 0 0 1 -5 mv / o c 2 0 0 1 0 -10 mv / o c 3 0 0 1 1 -15 mv / o c : : : : : : : : : : : : : : : : : : 12 1 1 0 0 -60 mv / o c 13 1 1 0 1 -65 mv / o c 14 1 1 1 0 -70 mv / o c 15 1 1 1 1 -75 mv / o c restriction
ST7669V ver 1.3 176/208 6/4/2008 register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (mtn[3:0]) power on sequence s/w reset h/w reset 1 st parameter 0xcc 2 nd parameter 0x09 3 rd parameter 0x01 4 th parameter 0x01 5 th parameter 0x23 6 th parameter 0x41 7 th parameter 0x61 8 th parameter 0xf3 flow chart
ST7669V ver 1.3 177/208 6/4/2008 9.1.74 thys : temperature detection threshold(f7h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex thys 0 1 0 1 1 1 1 0 1 1 1 (f7h) parameter 1 1 0 thys7 thys6 thys5 thys4 thys3 thys2 thys1 thys0 - note: - dont care description temperature detection threshold setting. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value d[7:0] power on sequence 02h s/w reset 02h h/w reset 02h flow chart
ST7669V ver 1.3 178/208 6/4/2008 9.1.75 frame set: frame pwm set (f9h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex frame1 set 0 1 0 1 1 1 1 1 0 0 1 (f9h) 1 st parameter 1 1 0 - - - p14 p13 p12 p11 p10 - 2 nd parameter 1 1 0 - - - p24 p23 p22 p21 p20 - : : : : : : : : : : : : - 15 th parameter 1 1 0 - - - p154 p153 p152 p151 p150 - 16 th parameter 1 1 0 - - - p164 p163 p162 p161 p160 - note: - dont care description this command is used to set frame pwm. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence -- s/w reset -- h/w reset -- flow chart
ST7669V ver 1.3 179/208 6/4/2008 10 specifications 10.1 absolute maximum ratings (v ss = 0v) item symbol value unit supply voltage 1 v dd - 0.3 ~ + 3.0 v supply voltage 2 v dd2,vdd3,vdd4,vdd5 - 0.3 ~ + 4.2 v supply voltage 3 v max (v0- xv0 ) - 0.3 ~ + 18.0 v input voltage range v in - 0.3 ~ v dd + 0.5 v output voltage range v o - 0.3 ~ v dd + 0.5 v operating temperature range t opr - 30 ~ + 85 c storage temperature range t stg - 40 ~ + 125 c note: (1). voltages are all based on vss = 0v. (2). voltage relationship: v0 vg vm vss xv0 must always be satisfied.
ST7669V ver 1.3 180/208 6/4/2008 11 dc characteristics 11.1 basic characteristics (v ss =0v, ta = -30 to 85c) parameter symbol conditions related pins min typ max unit logic operating voltage v ddi - *2) vdd 1.65 1.8 3.0 analog operating voltage v dda - *2) vdd2,3,4,5 2.4 2.75 3.3 driving voltage input v lcd v0 C xv0 *3) v0, xv0 - - 18.0 high level input voltage v ih *1) *2) 0.7v dd - v dd low level input voltage v il - *1) *2) v ss - 0.3v dd high level output voltage v oh i oh = -1.0ma 0.8v dd - v dd low level output voltage v ol i ol = +1.0ma *2) si, te v ss - 0.2v dd v input leakage current i il v in = v dd or v ss *1), *2) -1.0 - +1.0 a driver on resistance (seg) r onseg vg = 3.2v, ta = 25 c, v=10% s0 to s395 - 1 - driver on resistance (com) r oncom v0 = 16.0v, ta = 25 c v=10% c0 to c161 - 0.8 - k frame rate fr ta = 25c, n-line =0x8c, duty=162, fr=0x12 - - 77 - hz booster1 output voltage range v0 vdd2 - - 18 v reference voltage v ref ta = 25 c , no load - 1.75 1.8 1.85 v voltage follower output voltage vm ta = 25 c vm 0.7 vg/2 vdda-0.7 v booster2 output voltage range vg vg 1.8 - vddax2 v booster3 output voltage range xv0 xv0 vg-18 - - v note: *1) applies to if0, if1, /cs, /rst, /wr, /rd, a0 (s cl) and d15-d2, d1 (a0), d0 (si) pins *2) *3 )when the measurements are performed with lc d module, measurement points are like below.
ST7669V ver 1.3 181/208 6/4/2008 11.1.1 current consumption current consumption typical worst case operation mode condition idda (ma) iddi (ma) idda (ma) iddi (ma) - normal mode 1. checker board one by one pattern 2. vop=16.48v, n=0x8c, fr=77hz 0.45 0.1 0.9 0.2 - sleep in mode n/a 0.003 0.010 0.005 0.020 note: bare die note: 1. typical case: ta=25 , vdda=2.75v, vddi=1.8v. 2. worst case: ta=25 , vdda=2.4~3.3v, vddi=1.65~3.0v. 3. the current consumption is dc characteristics of st7 669v
ST7669V ver 1.3 182/208 6/4/2008 12 timing characteristics 12.1 parallel interface characteristics bus (8080- series mcu) figure 7.10.2-1 parallel interface characteristics bus (8080-series mcu) (v ss =0v, v ddi =1.80v, v dda =2.4v to 3.3v, ta = 25c) signal symbol parameter min max unit description t ast address setup time 10 - ns a0 t aht address hold time (write/read) 10 - ns - t chw chip select h pulse width 10 - ns t cs chip select setup time (write) 50 - ns t csh chip select hold time (write) 10 - ns t rcs chip select setup time (read id) 60 - ns t rcsfm chip select setup time (read fm) 60 - ns /cs t csf chip select wait time (write/read) 10 - ns t wc write cycle 160 - ns t wrh control pulse h duration 70 - ns /wr t wrl control pulse l duration 70 - ns t rc read cycle (id) 160 - ns t rdh control pulse h duration (id) 20 - ns /rd (id) t rdl control pulse l duration (id) 80 - ns when read id data t rcfm read cycle (fm) 250 - ns t rdhfm control pulse h duration (fm) 80 - ns /rd (fm) t rdlfm control pulse l duration (fm) 80 - ns when read from frame memory t dst data setup time 50 - ns t dht data hold time 0 - ns t ratfm read access time (fm) - 340 ns d[17:0] t odh output disable time 10 80 ns for maximum cl=30pf for minimum cl=8pf
ST7669V ver 1.3 183/208 6/4/2008 (v ss =0v, v ddi = 2.8v, v dda =2.4v to 3.3v, ta = 25c) signal symbol parameter min max unit description t ast address setup time 10 - ns a0 t aht address hold time (write/read) 10 - ns - t chw chip select h pulse width 0 - ns t cs chip select setup time (write) 30 - ns t csh chip select hold time (write) 10 - ns t rcs chip select setup time (read id) 60 - ns t rcsfm chip select setup time (read fm) 60 - ns /cs t csf chip select wait time (write/read) 10 - ns t wc write cycle 100 - ns t wrh control pulse h duration 50 - ns /wr t wrl control pulse l duration 50 - ns t rc read cycle (id) 140 - ns t rdh control pulse h duration (id) 20 - ns /rd (id) t rdl control pulse l duration (id) 60 - ns when read id data t rcfm read cycle (fm) 160 - ns t rdhfm control pulse h duration (fm) 50 - ns /rd (fm) t rdlfm control pulse l duration (fm) 60 - ns when read from frame memory t dst data setup time 30 - ns t dht data hold time 10 - ns t ratfm read access time (fm) - 340 ns d[17:0] t odh output disable time 10 80 ns for maximum cl=30pf for minimum cl=8pf figure 7.10.2-2 rising and falling timing for input and output signal figure 7.10.2-3 chip selection (/cs) timing
ST7669V ver 1.3 184/208 6/4/2008 figure 7.10.2-4 write to read and read to write tim ing note: the input signal rise time and fall time (tr, tf) is specified at 15 ns or less. logic high and low levels are specified as 30% and 70% of vdd for input signals.
ST7669V ver 1.3 185/208 6/4/2008 12.2 parallel interface characteristics bus (6800- series mcu) figure 7.10.2-1 parallel interface characteristics (6800-series mcu) (v ss =0v, v ddi =1.80v, v dda =2.4v to 3.3v, ta = 25c) signal symbol parameter min max unit description t ast address setup time 15 - ns a0 t aht address hold time (write/read) 15 - ns - t chw chip select h pulse width 10 - ns t cs chip select setup time (write) 50 - ns t rcs chip select setup time (read id) 50 - ns t rcsfm chip select setup time (read fm) 50 - ns t csf chip select wait time (write/read) 10 - ns /cs t csh chip select hold time 10 - ns t wc write cycle 160 - ns t wrh control pulse h duration 80 - ns /r/w t wrl control pulse l duration 80 - ns t rc read cycle (id) 130 - ns t rdh control pulse h duration (id) 30 - ns e (id) t rdl control pulse l duration (id) 20 - ns when read id data t rcfm read cycle (fm) 300 - ns t rdhfm control pulse h duration (fm) 40 - ns e (fm) t rdlfm control pulse l duration (fm) 80 - ns when read from frame memory t dst data setup time 50 - ns t dht data hold time 10 - ns t ratfm read access time (fm) - 340 ns d[17:0] t odh output disable time 10 80 ns for maximum cl=30pf for minimum cl=8pf
ST7669V ver 1.3 186/208 6/4/2008 (v ss =0v, v ddi =2.8v, v dda =2.4v to 3.3v , ta = 25c) signal symbol parameter min max unit description t ast address setup time 15 - ns a0 t aht address hold time (write/read) 15 - ns - t chw chip select h pulse width 10 - ns t cs chip select setup time (write) 30 - ns t rcs chip select setup time (read id) 30 - ns t rcsfm chip select setup time (read fm) 50 - ns t csf chip select wait time (write/read) 10 - ns /cs t csh chip select hold time 10 - ns t wc write cycle 100 - ns t wrh control pulse h duration 50 - ns r/w t wrl control pulse l duration 50 - ns t rc read cycle (id) 100 - ns t rdh control pulse h duration (id) 30 - ns e (id) t rdl control pulse l duration (id) 30 - ns when read id data t rcfm read cycle (fm) 150 - ns t rdhfm control pulse h duration (fm) 30 - ns e (fm) t rdlfm control pulse l duration (fm) 80 - ns when read from frame memory t dst data setup time 50 - ns t dht data hold time 10 - ns t ratfm read access time (fm) - 340 ns d[17:0] t odh output disable time 10 80 ns for maximum cl=30pf for minimum cl=8pf
ST7669V ver 1.3 187/208 6/4/2008 12.3 serial interface characteristics (3-pin seria l) figure 7.10.2-1 3-pin serial interface characterist ics (v ss =0v, v ddi =1.80v, v dda =2.4v to 3.3v, ta = 25c) signal symbol parameter min max unit description t chw /cs h pulse width 10 - ns t cssw /cs-scl setup time(write) 10 - ns /cs t cshw /cs-scl hold time(write) 15 - ns t scycw serial clock cycle (write) 130 - ns t shw scl h pulse width (write) 90 - ns scl t slw scl l pulse width (write) 40 - ns t sds data setup time 10 - ns si (din) (dout) t sdh data hold time 15 - ns (v ss =0v, v ddi =2.80v, v dda =2.4v to 3.3v, ta = 25c) signal symbol parameter min max unit description t chw /cs h pulse width 10 - ns t cssw /cs-scl setup time(write) 10 - ns /cs t cshw /cs-scl hold time(write) 15 - ns t scycw serial clock cycle (write) 80 - ns t shw scl h pulse width (write) 50 - ns scl t slw scl l pulse width (write) 30 - ns t sds data setup time 10 - ns si (din) (dout) t sdh data hold time 15 - ns
ST7669V ver 1.3 188/208 6/4/2008 12.4 serial interface characteristics (4-pin seria l) figure 7.10.2-1 4-pin serial interface characterist ics (v ss =0v, v ddi =1.80v, v dda =2.4v to 3.3v, ta = 25c) signal symbol parameter min max unit description t css chip select setup time 10 - ns t csh chip select hold time 15 - ns t scc chip select setup time 10 - ns /cs t chw chip select setup time 10 - ns t sas address setup time 15 - ns a0 t sah address hold time 15 - ns t scycw serial clock cycle (write) 130 - ns t shw scl h pulse width (write) 90 - ns scl t slw scl l pulse width (write) 40 - ns t sds data setup time 15 - ns si (din) (dout) t sdh data hold time 15 - ns (v ss =0v, v ddi = 2.80v, v dda =2.4v to 3.3v, ta = 25c) signal symbol parameter min max unit description t css chip select setup time 10 - ns t csh chip select hold time 15 - ns t scc chip select setup time 10 - ns /cs t chw chip select setup time 10 - ns t sas address setup time 15 - ns a0 t sah address hold time 15 - ns t scycw serial clock cycle (write) 80 - ns t shw scl h pulse width (write) 50 - ns scl t slw scl l pulse width (write) 30 - ns t sds data setup time 15 - ns si (din) (dout) t sdh data hold time 15 - ns
ST7669V ver 1.3 189/208 6/4/2008 12.5 output access/disable timing measurement meth od parallel interface (8080-series) serial interface (3-line) note: 1. pull-up/pull-down resistor: 3k 5% ; pull-up/pull-down capacitor: 8 or 30 pf 10% 2. capacitances and resistances of the oscilloscope s probe must be included externals components in t hese measurements.
ST7669V ver 1.3 190/208 6/4/2008 12.6 minimum value measurement parallel interface (8080-series) serial interface (3-line)
ST7669V ver 1.3 191/208 6/4/2008 12.7 maximum value measurement parallel interface (8080-series) serial interface (3-line)
ST7669V ver 1.3 192/208 6/4/2008 13 reset timing (v ss =0v, v ddi =1.65v to 3.0v, v dda =2.4v to 3.3v,ta = 25 c ) rating item signal symbol condition min. max. units reset l pulse width /rst trw 10 us 5 (*note 5) ms reset time trt 200 (*note 6,7) ms notes: 1. the reset cancel includes also required time for loading id bytes, vcom setting and other settings from eeprom (or similar device) to registers. this loading is done every time when there is hw reset cancel time (trt) within 5 ms after a rising edge of rst 2. spike due to an electrostatic discharge on rst l ine does not cause irregular system reset according to the table below: rst pulse action shorter than 5 s reset rejected longer than 9 s reset between 5 s and 9 s reset starts 3. during the resetting period, the display will be blanked (the display is entering blanking sequence , which maximum time is 120 ms, when reset starts in sleep out Cmod e. the display remains the blank state in sleep in -mode.) and then return to default condition for hardware reset. 4. spike rejection also applies during a valid rese t pulse as shown below:
ST7669V ver 1.3 193/208 6/4/2008 5. when reset applied during sleep in mode. 6. when reset applied during sleep out mode. 7. it is necessary to wait 5msec after releasing rs t before sending commands. also sleep out command c annot be sent for 120msec.
ST7669V ver 1.3 194/208 6/4/2008 14 instruction setup flow 14.1 command table -- 2 disable instruction flow 14.1.1 initial flow (command table -- 2 disable) n ote: about ST7669V initial code, please refer to i nitial ST7669V as below.
ST7669V ver 1.3 195/208 6/4/2008 14.1.2 burning flow (command table -- 2 ensable)
ST7669V ver 1.3 196/208 6/4/2008 void initial_ST7669V ( void ) { //-----------disable autoread + manual read once -- ----------------------------- write(command,0xd7); // auto load set write(data,0xdf); // auto load disable write(command,0xe0); // ee read/write mode write(data,0x00); // set read mode delayms(10); // delay 10ms write(command,0xe3); // read active delayms(20); // delay 20ms write(command,0xe1); // cancel control //---------------------------------- sleep out ---- ----------------------------------------- write(command, 0x11 ); // sleep out write(command, 0x28 ); // display off delayms(50); //delay 50ms //--------------------------------vop setting------ ------------------------------------------ write(command,0xc0); //set vop by initial module write(data, 0x42); //vop = 16.48v write(data, 0x01); // base on module //----------------------------set register--------- --------------------------------- write(command,0xc3); // bias select write(data,0x03); // 1/11 bias, base on module write(command,0xc4); // setting booster times write(data,0x07); // booster x 8 write(command,0xc5); // booster eff write(data,0x21); // be = 0x01 (level 2) write(command,0xcb); // vg with booster x2 control write(data,0x01); // vg from vdd2 write(command,0xcc); // set id1 code, depend on customer write(data,0x00); // write(command,0xce); // set id3 code, depend on customer write(data,0x00); write(command,0xb7); // com/seg direction for glass // write(data,0x48); // setting by lcd module
ST7669V ver 1.3 197/208 6/4/2008 write(command,0xd0); // analog circuit setting write(data,0x1d); // write(command, 0xb5 ); // n-line write(data, 0x8c); // non-rst, 13-line inversion write(command,0xd7); //auto read set write(data,0x9f); //otp disable write(command,0xb4); //ptl mode select write(data,0x18); //ptlmod normal mode write(command,0xbb); // read display data setting control write(data,0x26); // write(command,0xbc); // idle image saving mode write(data,0x04); write(command,0xbd); //display compensation step write(data,0x02; // step3 write(command,0x3a); // color mode = 65k write(data,0x05); // write(command,0x36); // memory access control // write(data,0xc8); // setting by lcd module write(command,0xb0); // duty = 160 duty write(data,0xa1); write(command,0x20); // display inversion off 1. set gamma table for module, please refer spec ch 9.1.73 . 2. set temp compensation for module, please refer sp ec ch 9.1.71 . write(command,0x2a); // col// write(data,0x00); // 0~127 write(data,0x00); write(data,0x00); write(data,0x7f); write(command,0x2b); // page // write(data,0x00); // 0~159 write(data,0x00); write(data,0x00); write(data,0x9f); write(command, 0x29 ); // display on }
ST7669V ver 1.3 198/208 6/4/2008 void set_otpc_register ( void ) { //--------------------------------set otpc register ---------------------------------------- write(command, 0xcd ); //set id2 code, depend on customer write(data, 0x80 ); write(command, 0xb5 ); // n-line write(data, 0x8c); // non-rst, 13-line inversion write(command,0xd0); // analog circuit setting write(data,0x1d); // write(command,0xd7); //auto read set write(data,0x9f); //otpb disable write(command,0xb4); //ptl mode select write(data,0x18); //ptlmod normal mode } void fine_tune_vop ( void ) { //------------------------------------- show map -- --------------------------------------------- show_image(); //display a image //------------------------------------ display on - ---------------------------------------------- write(command, 0x29 ); // display on //--------------------------------fine tune vop off set---------------------------------------- write( command, 0xc1); or write( command, 0xc2); //fine tuning vop here by command //0xc1(vopoffsetinc),0xc2(vopoffsetdec). note#1 }
ST7669V ver 1.3 199/208 6/4/2008 void otpc_writing ( void ) { //--------------------------------display off------ ---------------------------------- write(command, 0x28 ); // display off delayms(50); // delay 50ms //--------------------------------otp writing------ ---------------------------------- write( command, 0x00f0 ); // keep frame rate at 77hz write( data, 0x0012 ); write( data, 0x0012 ); write( data, 0x0012 ); write( data, 0x0012 ); write( command, 0x00e4 ); //otpc selection write( data, 0x0058 ); // select otpc write( command, 0x00e5 ); // set otpc writing setup write( data, 0x000e ); write( command, 0x00e0 ); // read/write mode setting write( data, 0x0020 ); // set write mode delayms(100); // delay 100ms write( command, 0x00e2 ); // write active delayms(100); // delay 100ms write( command, 0x00e1 ); // cancel control } note: #1 in this section+ & - key button, please exec ute write(command,0xc1) to increase one step at vop and execute write(command,0xc2) to decrease one step at vop, if necessary. #2 the tc is turn on in burning flow. if lcd module is too dark or bright, its an effect of backlight .
ST7669V ver 1.3 200/208 6/4/2008 15 power on flow
ST7669V ver 1.3 201/208 6/4/2008 15.1 power off flow
ST7669V ver 1.3 202/208 6/4/2008 16 ito /fpc layout guide 16.1 ito layout of power vdd, vdd2~vdd5, vss, vss1, vss2 & vss4: to avoid the noise in different power system affect other power system, please separate different powe r source on ito layout (vdd can be short together to get better performance). to reduce the ito resistance, the power source shou ld have enough trace width (includes ito width and fpc trace width). so the separated ito traces should be connec ted together by fpc. => the recommended solution is shown below. fpcpin fpcpin fpcpin fpcpin vdd3 vdd4 vdd5 icside vdd2 shortonfpc output, input and sensor of built-in power ci rcuits: the v0, xv0 and vg power circuits have output pins, in put pins and a sensor input. to avoid the power noi se affects the sensor input of internal power circuits. the tr ace should be separated by ito and should be connec ted together by fpc. so that the sensor pin has larger ito resist ance (for noise immunity). separated by ito short by ito
ST7669V ver 1.3 203/208 6/4/2008 the recommended layout topology is shown below: vpp: this is the power source for programming the intern al otp. if the ito resistance is too high, the oper ation current will cause the voltage drop while programming otp. please try to keep the ito resistance as low as poss ible.
ST7669V ver 1.3 204/208 6/4/2008 16.2 esd protection for esd protection of the lcm, here are some recomm endations: 1. rst (reset pin): please increase the resistance of this pin. here is an example: 2. esd protection ring: shielding ground is the first protection of esd. by connecting the blue (ito) ring to the fpc, the protection ring is finished. reset protection
ST7669V ver 1.3 205/208 6/4/2008 16.3 spi (3-line) ito suggestion in order to get good transfer quality, the si should have enough ito width to reduce the ito resistance (interface spi 3 line). the recommended layout topology is shown bel ow:
ST7669V ver 1.3 206/208 6/4/2008 17 application note 17.1 8080 series 8-bit parallel if[3:1] h h l cls h (internal osc) csel h c1 1uf/25v c2 1uf/16v c3 1uf/16v
ST7669V ver 1.3 207/208 6/4/2008 17.2 9-bit spi mode (3 line) if[3:1] l h l cls h (internal osc) csel h c1 1uf/25v c2 1uf/16v c3 1uf/16v
ST7669V ver 1.3 208/208 6/4/2008 ST7669V serial specification revision history version date description 1.0 2007/11/5 first issue 1.1 2007/12 remove 256 color 16bits mode. 1.2 2008/01 add ic thickness description modify example for set v0 at p48/p53 add t csh timing at 8080 interface table 1.3 2008/06 remove external clock function. remove un-necessary characteristics (p180/p181).

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